Page History
...
- Xilinx Artix-7 FPGA, U1
- 128K I2C CMOS serial EEPROM, U2
- Low-power programmable oscillator @25.000000 MHz, U3
- Cypress S26KS512S 512-Mbit (64-MByte) 1.8V HyperFlash™ memory, U4
- Low VIN high-efficiency step-down converter (1.5A max.), U5
- Low VIN high-efficiency step-down converter (1.5A max.), U6
- 1.8V, 256-MBit (32-MByte) quad SPI serial flash memory, U7
- Ultra-low supply-current voltage monitor with optional watchdog, U8
- 50-pin header placeholder for breadboard connector, J1
- 50-pin header placeholder for breadboard connector, J2
- 14-pin header placeholder for connector, J3
- JTAG/UART connector, JB1
- Red LED (SYSLED), D2
Initial Delivery State
I2C EEPROM | Empty |
Boot Process
Boot...
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
I/O signals connected to the SoCs I/O bank and B2B connector:
Bank | Type | B2B Connector | I/O Signal Count | Bank Voltage |
---|---|---|---|---|
34 | HR | J2 | 42 I/Os, 21 LVDS pairs | VCCIO34 |
35 | HR | J1 | 42 I/Os, 21 LVDS pairs | VCCIO35 |
Table x: General overview of PL I/O signals connected to the B2B connectors.
I/O Banks
Bank | VCCIO | B2B I/O | Notes | ||||
---|---|---|---|---|---|---|---|
0 | 3.3V | 0 | JTAG | ||||
14 | 3.3V | 0 (3) | 3 I/O in XMOD-JTAG - for use as UART | ||||
15 | 1.8V | 0 | used Used for optional hyper RAM | 16 | 2.5V | 0 | used for optional optical fiber transceiver |
34 | User select | 42 | 0R resistor option to select 3.3V | ||||
35 | User select | 42 | 0R resistor option to select 3.3V |
...
Overview
Content Tools