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Table 6: System Controller CPLD I/O pins.
DDR Memory
By default TE0841 module has two NT5AD256M16 DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Interface
Quad SPI interface is connected to the FPGA configuration bank 0.
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