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Table 6: System Controller CPLD I/O pins.

DDR Memory

By default TE0841 module has two NT5AD256M16 DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Interface

Quad SPI interface is connected to the FPGA configuration bank 0.

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For detailed information, refer to the reference page of the SC CPLD firmware of this module.

DDR Memory

By default TE0841 module has two NT5AD256M16 DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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