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Connected to FPGA JTAG, if JTAGEN is zero. J6 FMC JTAG connector is add into JTAG Chain, if PRSNT_TOP is zero and CPLD_IO1 is one. PRSNT_TOP has internal pulldown on CPLD and CPLD_IO1 internal pullup. FPGA IOs are flouting, if FPGA is not programmed.
JTAGEN | PRSNT_TOP | CPLD_IO1 | Description |
---|---|---|---|
1 | don't care | don't care | CPLD is in the JTAG Chain |
0 | 0 | 0 | Only Module FPGA is in the JTAG Chain |
0 | 0 | 1 | Module FPGA and FMC J6 are in the JTAG Chain. Note FMC J6 Chain must be closed. |
0 | 1 | 0 | Only Module FPGA is in the JTAG Chain |
0 | 1 | 1 | Only Module FPGA is in the JTAG Chain |
CPLD_IO2 is second module is present and CPLD_IO1 is one. otherwise it's zero.
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV01 | REV01 |
| Work REV01 working in progressprocess | ||||||||||||||||||||||
2017-09-09 | v.1 | REV01 | REV01 |
| Initial release | ||||||||||||||||||||||
All |
|
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