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Table of contents |
Overview
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General Design description
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Zynq PS Design with Linux for TE0701 with HDMI support.
Key Features
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- PetaLinux
- SD
- ETH
- USB
- I2C
- RTC
- VIO PHY LED
- HDMI
- TE0701
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Revision History
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Date | Vivado | Project Built | Authors | Description |
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2017-11-20 | 2017.2 | te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171122074701.zip te0720-test_board-vivado_2017.2-build_05_20171122074646.zip | John Hartfiel | |
Release Notes and Know Issues
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Issues | Description | Workaround | To be fixed version |
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HDMI | Not all HDMI Monitors are supported. Test Monitor: Samsung B2430L | -- | --- |
Requirements
Software
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Software | Version | Note |
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Vivado | 2017.2 | needed |
SDK | 2017.2 | needed |
PetaLinux | 2017.2 | needed |
Hardware
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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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te0720-03-2if | 2if | REV02, REV03 | 1GB | 32 |
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te0720-03-2ifc3 | 2if | REV02, REV03 | 1GB | 32 | 2.5 mm connector |
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te0720-03-2ifc8 | 2if | REV02, REV03 | 1GB | 32 | 32GB eMMC | |
te0720-03-1qf | 1qf | REV02, REV03 | 1GB | 32 |
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te0720-03-1cf | 1cf | REV02, REV03 | 1GB | 32 |
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te0720-03-2ef | 2ef | REV02, REV03 | 1GB | 32 |
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te0720-03-1cr | 1cr | REV02, REV03 | 256MB | 32 |
| Assembly variant need manual changes into FSBL and device tree template |
te0720-03-l1if | l1if | REV02, REV03 | 512MB (L) | 32 |
| Assembly variant need manual changes into FSBL and device tree template |
te0720-03-14s-1c | 14s | REV02, REV03 | 1GB (L) | 32 |
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Design supports following carriers:
Additional HW Requirements:
Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type |
Content
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For general structure and of the reference design, see Project Delivery
Design Sources
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Additional Sources
Prebuilt
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<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
Launch
Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Not used on this Example.
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Connect JTAG and power on PCB
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open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
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SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Connect HDMI to Monitor
- Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- I2C 1 Bus type: i2cdetect -y -r 1
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB: insert USB device
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
PHY LED:
System Design - Vivado
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Block Design
PS Interfaces
Type | Note |
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DDR | --- |
QSPI | MIO |
ETH0 | MIO |
USB0 | MIO |
SD0 | MIO |
SD1 | MIO |
UART0 | MIO |
UART1 | MIO |
I2C0 | EMIO TE0701 |
I2C1 | EMIO TE0720 |
GPIO | MIO |
TTC | EMIO |
Constrains
Basic module constrains
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language | ruby |
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title | _i_bitgen_common.xdc |
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#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design |
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language | ruby |
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title | _i_common.xdc |
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#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constrain
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language | ruby |
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title | _i_TE0720-SC.xdc |
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#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]
#
# If Bank 34 is not 2.5V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS25 [get_ports PL_pin*]
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language | ruby |
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title | _i_hdmi.xdc |
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#
# TE0701 I2C Bus
#
set_property PACKAGE_PIN W20 [get_ports iic_0_scl_io]
set_property PACKAGE_PIN W21 [get_ports iic_0_sda_io]
set_property IOSTANDARD LVCMOS25 [get_ports iic_0_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports iic_0_sda_io]
#
# ADV7511 Interface
#
set_property PACKAGE_PIN N20 [get_ports hdmi_out_clk]
set_property PACKAGE_PIN N19 [get_ports hdmi_out_de]
set_property PACKAGE_PIN R19 [get_ports hdmi_out_hsync]
set_property PACKAGE_PIN T19 [get_ports hdmi_out_vsync]
set_property PACKAGE_PIN T18 [get_ports {hdmi_out_data[0]}]
set_property PACKAGE_PIN R18 [get_ports {hdmi_out_data[1]}]
set_property PACKAGE_PIN R21 [get_ports {hdmi_out_data[2]}]
set_property PACKAGE_PIN R20 [get_ports {hdmi_out_data[3]}]
set_property PACKAGE_PIN M22 [get_ports {hdmi_out_data[4]}]
set_property PACKAGE_PIN K21 [get_ports {hdmi_out_data[5]}]
set_property PACKAGE_PIN M21 [get_ports {hdmi_out_data[6]}]
set_property PACKAGE_PIN J20 [get_ports {hdmi_out_data[7]}]
set_property PACKAGE_PIN T17 [get_ports {hdmi_out_data[8]}]
set_property PACKAGE_PIN J22 [get_ports {hdmi_out_data[9]}]
set_property PACKAGE_PIN T16 [get_ports {hdmi_out_data[10]}]
set_property PACKAGE_PIN J21 [get_ports {hdmi_out_data[11]}]
set_property IOSTANDARD LVCMOS25 [get_ports hdmi_*]
set_property PACKAGE_PIN AB16 [get_ports {cec_clk[0]}]
set_property PACKAGE_PIN AB17 [get_ports {ct_hpd[0]}]
set_property PACKAGE_PIN AA16 [get_ports {ls_oe[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {cec_clk[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ct_hpd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ls_oe[0]}]
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Software Design - SDK/HSI
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For SDK project creation, follow instructions from:
SDK Projects
Application
FSBL
TE modified 2017.2 FSBL
Functions:
- Read EEPROM MAC Address and make Address accessible by UBOOT (need defines on uboot platform-top.h)
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
- Configure ADV7511
- Configure Video Timing Controller core
- Configure VDMA core and enable transfers
Changes:
- Add adv7511.c, adv7511.h, vdma.c, vdma.h, te_fsbl_config.h, te_fsbl_hooks.h te_fsbl_hooks.c, and includ into fsbl_hooks.c
- te_fsbl_hooks.c defines must be changed for Assembly variant with smaller DDR size.
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
- Subsystem Auto Hardware Settings:Serial Settings: ps7_uart_0
U-Boot
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#include <configs/platform-auto.h>
#define UBOOT_ENV_MAGIC 0xCAFEBABE
#define UBOOT_ENV_MAGIC_ADDR 0xFFFFFC00
#define UBOOT_ENV_ADDR 0xFFFFFC04
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Device Tree
Device Tree HDMI entries must be changed for Assembly variant with smaller DDR size.
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/include/ "system-conf.dtsi"
/ {
};
/ {
memory { // Reduce memory for framebuffers
device_type = "memory";
reg = <0x0 0x3FC00000>; // Reduce memory for 1GB assembly variant
// reg = <0x0 0x1FC00000>; // Reduce memory for 1GB assembly variant
// reg = <0x0 0x0FC00000>; // Reduce memory for 1GB assembly variant
};
framebuffer0: framebuffer@0x3FC00000 { // HDMI out
compatible = "simple-framebuffer";
reg = <0x3FC00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
};
/*
framebuffer0: framebuffer@0x1FC00000 { // HDMI out
compatible = "simple-framebuffer";
reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
};
*/
/*
framebuffer0: framebuffer@0x0FC00000 { // HDMI out
compatible = "simple-framebuffer";
reg = <0x0FC00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
};
*/
};
&axi_vdma_0 {
status = "disabled";
};
&v_tc_0 {
//xilinx-vtc: probe of 43c20000.v_tc failed with error -2
status = "disabled";
};
/* default */
/* Flash */
&qspi {
flash0: flash@0 {
compatible = "w25q256";
};
};
/* ETH PHY */
&gem0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <0>;
};
};
};
/* USB PHY */
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
//compatible = "usb-nop-xceiv";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
dr_mode = "host";
//dr_mode = "peripheral";
usb-phy = <&usb_phy0>;
};
/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {
iexp@20 { // GPIO in CPLD
#gpio-cells = <2>;
compatible = "ti,pcf8574";
reg = <0x20>;
gpio-controller;
};
iexp@21 { // GPIO in CPLD
#gpio-cells = <2>;
compatible = "ti,pcf8574";
reg = <0x21>;
gpio-controller;
};
rtc@6F { // Real Time Clock
compatible = "isl12022";
reg = <0x6F>;
};
};
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Kernel
Activate:
- RTC_DRV_ISL12022
- CONFIG_FB_SIMPLE
- CONFIG_LOGO
- CONFIG_LOGO_LINUX_MONO
- CONFIG_LOGO_LINUX_VGA16
- CONFIG_LOGO_LINUX_CLUT224
Rootfs
Activate:
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Additional Software
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Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Legal Notices
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| IN:Legal Notices |
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| IN:Legal Notices |
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