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<!-- General Design description --> |
Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDKLinux with basic periphery of TE0808 Starterkit (TEBF0808 Carrier).
Key Features
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Revision History
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Design supports following carriers:
Carrier Model | Notes | Custom PCB | ||
---|---|---|---|---|
TEBF0808 | TEBF0808 | Used as reference carrier. | TEBT0808 | Change UART0 to UART1 (MIO68...69) and regenerate design |
Additional HW Requirements:
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Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Additional Sources
Type | Location | Notes |
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Prebuilt
SI5345 | <design name>/misc/Si5345 | SI5345 Project with current PLL Configuration |
Prebuilt
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<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
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Reference Design is available on:
Design Flow
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- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Use Board Part Files, which ends with *_tebf0808
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
Launch
Programming
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Description of Block Design, Constrains...
BD Pictures from Export...
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Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
Launch
Programming
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Description of Block Design, Constrains...
BD Pictures from Export...
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Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
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Example:
Connect JTAG and power on PCB
(if not done) Select
correct device and Xilinx install path on "design_basic_settings.cmd"
and create Vivado project with "vivado_create |
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<!--
Example:
Connect JTAG and power on PCB
(if not done) Select
correct device and Xilinx install path on "design_basic_settings.cmd"
and create Vivado project with "vivado_create_project_guimode.cmd" or
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
--> |
- Select JTAG as Boot Mode (see Carrier Description and ZynqMP TRM)
- Connect JTAG to Host PC
- Power On
- Open Vivado Hardware Manager with Auto Connect
- Right Click to FPGA Device XCU... and select Add Configuration Memory Device
- Select correct Flash Typ (see schematics or FPGAFLASHTYP on test_board/board_files/TE0808_board_files.csv)
- Open Program Configuration Memory Device
- Configuration file: test_board/prebuilt/boot_image/<short dir>/hello_te0808/Boot.bin
- Zynq FSBL: test_board/prebuilt/software/<short dir>/zynqmp_fsbl.elf
- Program Device Flash
Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP
SD
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with SDK Debugger into device, see:
Usage
QSPI Boot:
Not used on this Example.
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 46041551 Programming
- Connect UART USB (most cases same as JTAG XMOD)
- Select QSPI SD Card as Boot Mode
Note: See TRM of the Carrier, which is used. - (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect Sata Disc
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional) Connect Network Cable
- Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI SD into OCM, 2. FSBL loads Application into DDR
Debugging:
System Design - Vivado
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Description of Block Design, Constrains...
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Block Design
PS Interfaces
Activated interfaces:
...
- ATF(bl31.elf) and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR.
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB device
- PCIe type "lspci"
Vivado Hardware Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
RGPIO Interface:
- Set Bit 31-28 to "1010" to activat RGPIO Interface of Master or Slave CPLD.
- Description: TEBF0808 Master CPLD#RGPIO, TEBF0808 Slave CPLD#RGPIO
- Set Bit 31-28 to "1010" to activat RGPIO Interface of Master or Slave CPLD.
- LED Control:
- XMOD 2(without green dot) and HD LED are accessible.
- XMOD 2(without green dot) and HD LED are accessible.
System Design - Vivado
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Description of Block Design, Constrains...
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Block Design
PS Interfaces
Activated interfaces:
Type | Note |
---|---|
DDR | |
QSPI | MIO |
SD0 | MIO |
SD1 | MIO |
CAN0 | EMIO |
I2C0 | MIO |
PJTAG0 | MIO |
UART0 | MIO |
GPIO0 | MIO |
TTC0 | |
GEM3 | MIO |
USB0 | MIO/GTP |
PCIe | MIO/GTP |
SATA | GTP |
Constrains
Basic module constrains
Code Block | ||||
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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#set_property PACKAGE_PIN AH6 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
#
#set_property PACKAGE_PIN G8 [get_ports {B230_CLK0_clk_p[0]}]
#set_property PACKAGE_PIN J8 [get_ports {B229_CLK1_clk_p[0]}]
#
#set_property PACKAGE_PIN F25 [get_ports {B128_CLK0_clk_p[0]}]
#LED_HD SC0 J3:31
set_property PACKAGE_PIN J14 [get_ports {LED_HD[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED_HD[0]}]
#LED_XMOD SC17 J3:48
set_property PACKAGE_PIN B13 [get_ports {LED_XMOD2[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED_XMOD2[0]}]
#System Controller IP
set_property PACKAGE_PIN A15 [get_ports base_sc10_io]
set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports base_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
# PLL
#set_property PACKAGE_PIN AH6 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
# Clocks
#set_property PACKAGE_PIN J8 [get_ports {B229_CLK1_clk_p[0]}]
set_property PACKAGE_PIN F25 [get_ports {B128_CLK0_clk_p[0]}]
# SFP
#set_property PACKAGE_PIN G8 [get_ports {B230_CLK0_clk_p}]
# B230_RX3_P
#set_property PACKAGE_PIN A4 [get_ports {SFP1_rxp}]
# B230_TX3_P
#set_property PACKAGE_PIN A8 [get_ports {SFP1_txp}]
# B230_RX2_P
#set_property PACKAGE_PIN B2 [get_ports {SFP2_rxp}]
# B230_TX2_P
#set_property PACKAGE_PIN B6 [get_ports {SFP2_txp}]
# Audio Codec
#LRCLK J3:49 B47_L9_N
#BCLK J3:51 B47_L9_P
#DAC_SDATA J3:53 B47_L7_N
#ADC_SDATA J3:55 B47_L7_P
set_property PACKAGE_PIN G14 [get_ports LRCLK ]
set_property PACKAGE_PIN G15 [get_ports BCLK ]
set_property PACKAGE_PIN E15 [get_ports DAC_SDATA ]
set_property PACKAGE_PIN F15 [get_ports ADC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
# CAN
#CAN RX SC19 J3:52 B47_L2_P
#CAN TX SC18 J3:50 B47_L2_N
#CAN S SC16 J3:46 B47_L3_N
set_property PACKAGE_PIN A13 [get_ports CAN_0_S ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_S ]
set_property PACKAGE_PIN B14 [get_ports CAN_0_rx ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_rx ]
set_property PACKAGE_PIN A14 [get_ports CAN_0_tx ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_tx ]
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Software Design - SDK/HSI
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optional chapter
separate sections for different apps
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For SDK project creation, follow instructions from:
Application
FSBL
TE modified 2017.2 FSBL
Changes:
- Si5345Configuration, PCIe Reset over GPIO see xfsbl_board.c and xfsbl_board.h
- Add Si5345-Registers.h, si5345.c, si5345.h
PMU
Xilinx default PMU firmware.
Hello TE0808
Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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optional chapter
Add "No changes." or "Activate: List"
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For PetaLinux installation and project creation, follow instructions from:
Config
No changes.
U-Boot
- Change platform-top.h
Code Block | ||
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#include <configs/platform-auto.h>
/* Extra U-Boot Env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
SERIAL_MULTI \
CONSOLE_ARG \
PSSERIAL0 \
"nc=setenv stdout nc;setenv stdin nc;\0" \
"ethaddr=00:0a:35:00:22:01\0" \
"importbootenv=echo \"Importing environment from SD ...\"; " \
"env import -t ${loadbootenv_addr} $filesize\0" \
"loadbootenv=load mmc $sdbootdev:$partid ${loadbootenv_addr} ${bootenv}\0" \
"sd_uEnvtxt_existence_test=test -e mmc $sdbootdev:$partid /uEnv.txt\0" \
"uenvboot=" \
"if run sd_uEnvtxt_existence_test; then" \
"run loadbootenv" \
"echo Loaded environment from ${bootenv};" \
"run importbootenv; \0" \
"sdboot=echo boot Petalinux; run uenvboot ; mmcinfo && fatload mmc 1 ${netstart} ${kernel_img} && bootm \0" \
"autoload=no\0" \
"clobstart=0x10000000\0" \
"netstart=0x10000000\0" \
"dtbnetstart=0x11800000\0" \
"loadaddr=0x10000000\0" \
"boot_img=BOOT.BIN\0" \
"load_boot=tftpboot ${clobstart} ${boot_img}\0" \
"update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot ${installcmd}; setenv img; setenv psize; setenv installcmd\0" \
"install_boot=mmcinfo && fatwrite mmc 1 ${clobstart} ${boot_img} ${filesize}\0" \
"bootenvsize=0x40000\0" \
"bootenvstart=0x100000\0" \
"eraseenv=sf probe 0 && sf erase ${bootenvstart} ${bootenvsize}\0" \
"jffs2_img=rootfs.jffs2\0" \
"load_jffs2=tftpboot ${clobstart} ${jffs2_img}\0" \
"update_jffs2=setenv img jffs2; setenv psize ${jffs2size}; setenv installcmd \"install_jffs2\"; run load_jffs2 test_img; setenv img; setenv psize; setenv installcmd\0" \
"sd_update_jffs2=echo Updating jffs2 from SD; mmcinfo && fatload mmc 1:1 ${clobstart} ${jffs2_img} && run install_jffs2\0" \
"install_jffs2=sf probe 0 && sf erase ${jffs2start} ${jffs2size} && " \
"sf write ${clobstart} ${jffs2start} ${filesize}\0" \
"kernel_img=image.ub\0" \
"load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \
"update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel ${installcmd}; setenv img; setenv psize; setenv installcmd\0" \
"install_kernel=mmcinfo && fatwrite mmc 1 ${clobstart} ${kernel_img} ${filesize}\0" \
"cp_kernel2ram=mmcinfo && fatload mmc 1 ${netstart} ${kernel_img}\0" \
"dtb_img=system.dtb\0" \
"load_dtb=tftpboot ${clobstart} ${dtb_img}\0" \
"update_dtb=setenv img dtb; setenv psize ${dtbsize}; setenv installcmd \"install_dtb\"; run load_dtb test_img; setenv img; setenv psize; setenv installcmd\0" \
"sd_update_dtb=echo Updating dtb from SD; mmcinfo && fatload mmc 1:1 ${clobstart} ${dtb_img} && run install_dtb\0" \
"fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \
"test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \
"test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \
"netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \
"default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \
"" |
Device Tree
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/include/ "system-conf.dtsi"
/ {
};
/* default */
/* SD */
&sdhci1 {
// disable-wp;
no-1-8-v;
};
/* ETH PHY */
&gem3 {
phy-handle = <&phy0>;
phy0: phy0@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
/* QSPI */
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
// compatible = "n25q256a";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
/* I2C */
&i2c0 {
i2cswitch@73 { // u
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
i2c@2 { // PCIe
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 { // i2c SFP
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c@4 { // i2c SFP
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 { // i2c EEPROM
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 { // i2c FMC
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
si570_2: clock-generator3@5d {
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <78800000>;
};
};
i2c@7 { // i2c USB HUB
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
i2cswitch@77 { // u
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
i2c-mux-idle-disconnect;
i2c@0 { // i2c PMOD
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 { // i2c Audio Codec
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/*
adau1761: adau1761@38 {
compatible = "adi,adau1761";
reg = <0x38>;
};
*/
};
i2c@2 { // i2c FireFly A
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 { // i2c FireFly B
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c@4 { // i2c PLL
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 { // i2c SC
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 { // i2c
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
i2c@7 { // i2c
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/* UNUSED DMA disable */
&lpd_dma_chan1 {
status = "disabled";
};
&lpd_dma_chan2 {
status = "disabled";
};
&lpd_dma_chan3 {
status = "disabled";
};
&lpd_dma_chan4 {
status = "disabled";
};
&lpd_dma_chan5 {
status = "disabled";
};
&lpd_dma_chan6 {
status = "disabled";
};
&lpd_dma_chan7 {
status = "disabled";
};
&lpd_dma_chan8 {
status = "disabled";
};
|
Kernel
No changes.
Rootfs
Activate:
- i2c-tools
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
adau1761init
Audio initialisation
Constrains
Basic module constrains
Code Block | ||||
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Not needed.
Software Design - SDK/HSI
HTML |
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<!--
optional chapter
separate sections for different apps
--> |
For SDK project creation, follow instructions from:
Application
FSBL
Xilinx default FSBL
Hello TE0808
Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Software
HTML |
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<!--
Add Description for other Software, for example SI CLK Builder ...
--> |
...
--> |
SI5345
Download ClockBuilder Pro for SI5345
- Install and start ClockBuilder
- Open "/misc/SI5345/Si5345-RevB-0808-02A-Project.slabtimeproj"
- Modify settings
- Export → Register File → select C code header → save to file
- Replace Header files from FSBL template with generated file
Appx. A: Change History and Legal Notices
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Date | Document Revision | Authors | Description | ||||||||||||||||||||||
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2017-11-22 | v.10 | John Hartfiel |
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2017-11-14 | v.6 | John Hartfiel
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