Page History
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Table of contents
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Overview
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Linux with basic periphery of TE0808 Starterkit (TEBF0808 Carrier).
Key Features
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Revision History
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Date | Vivado | Project Built | Authors | Description |
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2018-01-15 | 2017.4 | TE0808-StarterKit-vivado_2017.4-build_03_20180115092306.zip | John Hartfiel |
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2017-12-18 | 2017.2 | TE0808-StarterKit_noprebuilt-vivado_2017.2-build_07_20171219151749.zip TE0808-StarterKit-vivado_2017.2-build_07_20171219151728.zip | John Hartfiel |
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Release Notes and Know Issues
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
Requirements
Software
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Software | Version | Note |
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Vivado | 2017.4 | needed |
SDK | 2017.4 | needed |
PetaLinux | 2017.4 | needed |
Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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TE0808-ES1 | es1 | REV02, REV03 | 2GB | 64MB | ||
TE0808-ES2 | es2 | REV03, REV04 | 2GB | 64MB | ||
TE0808-2ES2 | 2es2 | REV03, REV04 | 2GB | 64MB | ||
TE0808-04-09EG-1EA | 9eg_1ea | REV04 | 2GB | 64MB | ||
TE0808-04-09EG-1EB | 9eg_1eb | REV04 | 4GB | 64MB | ||
TE0808-04-09EG-1ED | 9eg_1eb | REV04 | 4GB | 64MB | 2,5 mm connector | |
TE0808-04-09EG-1EE | 9eg_1eb | REV04 | 4GB | 128MB | ||
TE0808-04-09EG-1EL | 9eg_1eb | REV04 | 4GB | 128MB | 2,5 mm connector | |
TE0808-04-09EG-2IB | 9eg_2ib | REV04 | 4GB | 64MB | ||
TE0808-04-09EG-2IE | 9eg_2ib | REV04 | 4GB | 128MB | ||
TE0808-04-15EG-1EB | 15eg_1eb | REV04 | 4GB | 64MB | ||
TE0808-04-15EG-1EE | 15eg_1eb | REV04 | 4GB | 128MB |
Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.
Design supports following carriers:
Carrier Model | Notes |
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TEBF0808 | Used as reference carrier. |
Additional HW Requirements:
Additional Hardware | Notes |
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Content
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For general structure and of the reference design, see Project Delivery
Design Sources
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Additional Sources
Type | Location | Notes |
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SI5345 | <design name>/misc/Si5345 | SI5345 Project with current PLL Configuration |
Prebuilt
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which ends with *_tebf0808
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
Launch
Programming
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Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup - Copy image.ub on SD-Card
- Insert SD-Card
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (JTAG XMOD)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect Sata Disc
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional) Connect Network Cable
- Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB device
- PCIe type "lspci"
Vivado Hardware Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
RGPIO Interface:
- Set Bit 31-28 to "1010" to activat RGPIO Interface of Master or Slave CPLD.
- Description: TEBF0808 Master CPLD#RGPIO, TEBF0808 Slave CPLD#RGPIO
- Set Bit 31-28 to "1010" to activat RGPIO Interface of Master or Slave CPLD.
- LED Control:
- XMOD 2(without green dot) and HD LED are accessible.
- XMOD 2(without green dot) and HD LED are accessible.
System Design - Vivado
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Block Design
PS Interfaces
Activated interfaces:
Type | Note |
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DDR | |
QSPI | MIO |
SD0 | MIO |
SD1 | MIO |
CAN0 | EMIO |
I2C0 | MIO |
PJTAG0 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0..1 | |
TTC0..3 | |
GEM3 | MIO |
USB0 | MIO/GTP |
PCIe | MIO/GTP |
SATA | GTP |
Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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#LED_HD SC0 J3:31 set_property PACKAGE_PIN J14 [get_ports {LED_HD[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {LED_HD[0]}] #LED_XMOD SC17 J3:48 set_property PACKAGE_PIN B13 [get_ports {LED_XMOD2[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {LED_XMOD2[0]}] #System Controller IP set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io] set_property PACKAGE_PIN B15 [get_ports BASE_sc11] set_property PACKAGE_PIN C13 [get_ports BASE_sc12] set_property PACKAGE_PIN C14 [get_ports BASE_sc13] set_property PACKAGE_PIN E13 [get_ports BASE_sc14] set_property PACKAGE_PIN E14 [get_ports BASE_sc15] set_property PACKAGE_PIN G13 [get_ports BASE_sc5] set_property PACKAGE_PIN J15 [get_ports BASE_sc6] set_property PACKAGE_PIN K15 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] # PLL #set_property PACKAGE_PIN AH6 [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}] # Clocks #set_property PACKAGE_PIN J8 [get_ports {B229_CLK1_clk_p[0]}] #set_property PACKAGE_PIN F25 [get_ports {B128_CLK0_clk_p[0]}] # SFP #set_property PACKAGE_PIN G8 [get_ports {B230_CLK0_clk_p}] # B230_RX3_P #set_property PACKAGE_PIN A4 [get_ports {SFP1_rxp}] # B230_TX3_P #set_property PACKAGE_PIN A8 [get_ports {SFP1_txp}] # B230_RX2_P #set_property PACKAGE_PIN B2 [get_ports {SFP2_rxp}] # B230_TX2_P #set_property PACKAGE_PIN B6 [get_ports {SFP2_txp}] # Audio Codec #LRCLK J3:49 B47_L9_N #BCLK J3:51 B47_L9_P #DAC_SDATA J3:53 B47_L7_N #ADC_SDATA J3:55 B47_L7_P set_property PACKAGE_PIN G14 [get_ports LRCLK ] set_property PACKAGE_PIN G15 [get_ports BCLK ] set_property PACKAGE_PIN E15 [get_ports DAC_SDATA ] set_property PACKAGE_PIN F15 [get_ports ADC_SDATA ] set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ] set_property IOSTANDARD LVCMOS18 [get_ports BCLK ] set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ] set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ] # CAN #CAN RX SC19 J3:52 B47_L2_P #CAN TX SC18 J3:50 B47_L2_N #CAN S SC16 J3:46 B47_L3_N set_property PACKAGE_PIN A13 [get_ports CAN_0_S ] set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_S ] set_property PACKAGE_PIN B14 [get_ports CAN_0_rx ] set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_rx ] set_property PACKAGE_PIN A14 [get_ports CAN_0_tx ] set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_tx ] |
Software Design - SDK/HSI
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For SDK project creation, follow instructions from:
Application
FSBL
TE modified 2017.4 FSBL
Changes:
- Si5345Configuration, PCIe Reset over GPIO see xfsbl_board.c and xfsbl_board.h
- Add Si5345-Registers.h, si5345.c, si5345.h
zynqmp_fsbl_flash
TE modified 2017.4 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
PMU
Xilinx default PMU firmware.
Hello TE0808
Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
No changes.
U-Boot
- Change platform-top.h
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#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ "image.ub ram $netstart 0x1e00000\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" #define DFU_ALT_INFO \ DFU_ALT_INFO_RAM /*Required for uartless designs */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #ifdef CONFIG_DEBUG_UART #undef CONFIG_DEBUG_UART #endif #endif /*select sd instead of mmc for autoboot */ #define CONFIG_BOOTCOMMAND "run uenvboot; mmcinfo && fatload mmc 1 ${netstart} ${kernel_img};bootm ${netstart}" |
Device Tree
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/include/ "system-conf.dtsi" / { }; /* default */ /* SD */ &sdhci1 { // disable-wp; no-1-8-v; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { // compatible = "n25q256a"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* I2C */ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // i2c SFP #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { // i2c SFP #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // i2c EEPROM #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { // i2c FMC #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_2: clock-generator3@5d { #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <78800000>; }; }; i2c@7 { // i2c USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // i2c PMOD #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // i2c FireFly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // i2c FireFly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { // i2c PLL #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // i2c SC #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { // i2c #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // i2c #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* UNUSED DMA disable */ &lpd_dma_chan1 { status = "disabled"; }; &lpd_dma_chan2 { status = "disabled"; }; &lpd_dma_chan3 { status = "disabled"; }; &lpd_dma_chan4 { status = "disabled"; }; &lpd_dma_chan5 { status = "disabled"; }; &lpd_dma_chan6 { status = "disabled"; }; &lpd_dma_chan7 { status = "disabled"; }; &lpd_dma_chan8 { status = "disabled"; }; |
Kernel
No changes.
Rootfs
Activate:
- i2c-tools
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
adau1761init
Audio initialisation.
Additional Software
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SI5345
Download ClockBuilder Pro for SI5345
- Install and start ClockBuilder
- Open "/misc/SI5345/Si5345-RevB-0808-02A-Project.slabtimeproj"
- Modify settings
- Export → Register File → select C code header → save to file
- Replace Header files from FSBL template with generated file
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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