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Firmware for PCB CPLD with designator U18. CPLD Device in Chain: LCMX02-256HC

Feature Summary

  • Reset
  • JTAG
  • PUD_C
  • LED
  • Power Management
  • Rest

Firmware Revision and supported PCB Revision

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Name / opt. VHD NameDirectionPinDescription
CPLD_IO / XIO inin17 FPGA Bank 45 P28
DONEin13FPGA Configuration DONE_0 Pin
EN_PL
20(currently internal DCDC Pullup is used to enable power) / currently_not_used
F_TCK / C_TCKout8JTAG to FPGA
F_TDI / C_TDIout10JTAG to FPGA
F_TDO / C_TDOin11JTAG to FPGA
F_TMS / C_TMSout9JTAG to FPGA
INIT_Bin16FPGA INIT_B / currently_not_used
JTAGMODEin26Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to moduleFPGA, one: CPLD access)
 / LED1out4green LED D1
N.C. / dummyout5dummy pin
nRST_SC0 / RESINin21B2B Reset_N
PROG_Bout12FPGA Configuration PROGRAM_B_0 Pin
PUDC_Bout14FPGA PUDC_B
SC1
23B2B JM1-32 / currently_not_used
SC2
25B2B JM1-30 / currently_not_used
SC3
27B2B JM1-28 / currently_not_used
SC4
28B2B JM1-7 / currently_not_used
TCK / M_TCKin30JTAG from B2B connector
TDI / M_TDIin32JTAG from B2B connector
TDO / M_TDOout1JTAG from B2B connector
TMS / M_TMSin29JTAG from B2B connector

 

Functional Description

JTAG

Power

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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).

Reset

RESIN is connected to PROG_B.

PUD_C

PUD_C is set to zero.

LED

Green LED D1.

StatusPriorityDescription
ON1B2B Reset is set
Blinking2Don is low (FPGA not programmed)
User Defined3XIO is connected to LED


Appx. A: Change History and Legal Notices

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.


 

  REV01  REV01

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modified-user

Work in progress


REV01 , Firmware released  2016-11-02
2018-03-142017-06-07

v.191

  REV01  REV01

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created-user
created-user

Initial release
 All  

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modified-users

 

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