Page History
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Date | Vivado | Project Built | Authors | Description |
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2018-04-12 | 2017.4 | te0712-test_board-vivado_2017.4-build_07_20180412081225.zip te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip | John Hartfiel |
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2018-03-28 | 2017.4 | te0712-test_board-vivado_2017.4-build_07_20180328145151.zip te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zip | John Hartfiel |
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2018-01-08 | 2017.4 | te0712-test_board-vivado_2017.4-build_02_20180108155712.zip te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zip | John Hartfiel |
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2017-12-15 | 2017.2 | te0712-test_board-vivado_2017.2-build_07_20171215172447.zip te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zip | John Hartfiel |
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2017-11-07 | 2017.2 | te0712-test_board-vivado_2017.2-build_05_20171107172917.zip te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zip | John Hartfiel |
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2017-10-05 | 2017.2 | te0712-test_board-vivado_2017.2-build_03_20171005082148.zip te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zip | John Hartfiel |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes | |
---|---|---|---|---|---|---|---|
te0712-02-35-2i | 35_2i | REV02 | 1GB | 32MB | |||
te0712-02-100-1i | 100_1i | REV01, REV02 | 1GB | 32MB | |||
te0712-02-100-2c | 100_2c | REV01, REV02 | 1GB | 32MB | |||
te0712-02-100-2c3 | 100_2c | REV01, REV02 | 1GB | 32MB | 2,5 mm connector | ||
te0712-02-100-2ca | 100_2ca | REV02 | 1GB | 32MB | Micron QSPI Flash | ||
te0712-02-200-1i | 200_1i | REV01, REV02 | 1GB | 32MB | |||
te0712-02-200-1i3 | 200_1i | REV01, REV02 | 1GB | 32MB | 2,5 mm connector | ||
te0712-02-200-2i | 200_2i | REV01, REV02 | 1GB | 32MB | |||
te0712-02-200-2c | 200_2c | REV01, REV02 | 1GB | 32MB | |||
te0712-02-200-2c3 | 200_2c | REV01, REV02 | 1GB | 32MB | 2,5 mm connector |
Design supports following carriers:
Carrier Model | Notes |
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TE0701 | |
TE0703 | used as reference carrier |
TE0705 | |
TE0706 | |
TEBA0841 |
Additional HW Requirements:
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Type | Location | Notes | |
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SI5338 Project | \misc\SI5338 |
Prebuilt
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<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
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TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition)
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- Generate UBoot SREC:
- Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
- Create "uboot-dummy" application
Note: Use Hello World Example - Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
- Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
- Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
- Press Apply or regenerate project
Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
- Generate MCS Firmware (optional):
- Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
- Create "SCU" application
Note: Select MCS Microblaze and SCU Application - Select Release Built
- Regenerate App
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
- Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into "\firmware\microblaze_0\"
- (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into "\firmware\microblaze_mcs_0\"
- Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"
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- Prepare HW like described on section Programming 43679821
- Connect UART USB (most cases same as JTAG)
- Power on PCB
Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR
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- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz - MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
- Additional Infos: System reset from MCS and GIO outputs
- Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
System Design - Vivado
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<!-- Description of Block Design, Constrains... BD Pictures from Export... --> |
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Code Block | ||||||||
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#I2C set_property PACKAGE_PIN W21 [get_ports PLL_I2C_scl_io] set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_scl_io] set_property PACKAGE_PIN T20 [get_ports PLL_I2C_sda_io] set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io] #Reset set_property PACKAGE_PIN T3 [get_ports reset] set_property IOSTANDARD LVCMOS15 [get_ports reset] #CLKS set_property PACKAGE_PIN R4 [get_ports {CLK1B[0]}] set_property IOSTANDARD SSTL15LVCMOS15 [get_ports {CLK1B[0]}] set_property PACKAGE_PIN K4 [get_ports {CLK0_clk_p[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK0_clk_p[0]}] #ETH PHY set_property PACKAGE_PIN N17 [get_ports phy_rst_n] set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n] |
Code Block | ||||||||
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create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_ports mgt_clk0_clk_p] create_clock -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports {CLK0_clk_p[0]}] create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports {CLK1B[0]}] create_clock -period 15.152 -name msys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_12_GEN.SCK_MISO_STARTUP_USED.QSPI_STARTUP_BLOCK_I/cfgmclk -waveform {0.000 7.576} [get_pins msys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_12_GEN.SCK_MISO_STARTUP_USED.QSPI_STARTUP_BLOCK_I/STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK] set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_i] set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i] set_false_path -from [get_clocks msys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_12_GEN.SCK_MISO_STARTUP_USED.QSPI_STARTUP_BLOCK_I/cfgmclk] -to [get_clocks clk_pll_i] set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p] set_false_path -from [get_pinsclocks msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLKclk_pll_i] -to [get_pinsclocks {msys_i/vioutil_ds_buf_0/instU0/PROBE_IN_INST/probe_in_reg_reg[*]/DIBUF_OUT[0]}] set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}] set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_FREFCLK_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmetervio_0/U0inst/F_reg[*]/D}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CECARRYINPROBE_IN_INST/probe_in_reg_reg[*]/D}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEP}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEA2}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEB2}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEALUMODE}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CECTRL}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEC}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTC}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTB}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTA}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTP}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTINMODE}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTALUMODE}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTCTRL}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/CCLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETERF_genreg[*].COUNTER_F_inst/bl.DSP48E_2/RSTALLCARRYIN}]/D}] |
Software Design - SDK/HSI
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U-Boot
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#include <configs/platform-auto.h>
#undef CONFIG_PHY_XILINX
#undef XILINX_EMACLITE_BASEADDR 0x40E00000
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#undef CONFIG_PHY_MARVELL
#undef CONFIG_PHY_NATSEMI
#undef CONFIG_NET_MULTI
#undef CONFIG_BOOTP_MAY_FAIL
#undef CONFIG_NETCONSOLE 1
#undef CONFIG_SERVERIP 192.168.150.117
#undef CONFIG_IPADDR
/* PREBOOT */
#define CONFIG_PREBOOT "echo U-BOOT for petalinux;setenv preboot; echo; "
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v.22 | John Hartfiel |
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2018-02-13 | v.19 | John Hartfiel |
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2018-01-08 | v.16 | John Hartfiel |
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2017-12-15 | v.15 | John Hartfiel |
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2017-11-07 | v.11 | John Hartfiel |
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2017-10-06 | v.10 | John Hartfiel |
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2017-10-05 | v.8 | John Hartfiel |
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2017-09-11 | v.1 |
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