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The TEB0911 Ultrarack+ offers 6FMC (FPGA Mezzanine Card) connectors with high pin count (HPC) which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
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Figure x: General overview of the FMC HPC connectors
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MGT Lanes
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Table x: MGT reference clock sources.
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XMOD Interface
JTAG access to the ... is provided through B2B connector ....
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Table 5: JTAG interface signals.
System Controller CPLD I/O Pins
Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
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Gigabit Ethernet Interface
USB3.0 Interface
SFP+ Interface
SSD Interface
DisplayPort Interface
DDR4 Memory Socket
CAN Interface
SD Card Interface
Describe SD Card interface shortly here if the module has one...
FPGA / SoC Pin | Connected To | Signal Name | Notes |
---|---|---|---|
MIO0 | J10-9 | Card detect switch | |
MIO10 | J10-7 | DAT0 | |
MIO11 | J10-3 | CMD | |
MIO12 | J10-5 | CLK | |
MIO13 | J10-8 | DAT1 | |
MIO14 | J10-1 | DAT3 | |
MIO15 | J10-2 | CD/DAT3 |
Table x: SD Card interface signals and connections.
PLL Clock Programing Interface
4-Wire PWM FAN Connectors
SMA Coax Clock Input
On-board Peripherals
Table x: System Controller CPLD I/O pins.
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Quad SPI Interface
Following line is just an example, change it to your needs.
Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
Note that table column says "Signal Name", it should match the name used on the schematic.
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PLL, PHY...
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System Controller CPLD
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed information, refer to the reference page of the SC CPLD firmware of this module.
The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27.
The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank differential lanes and I²C interface.
The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.
Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO), PL bank pins and I²C interface.
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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
Pin Name | Mode | Function | B2B Connector Pin | Default Configuration |
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PGOOD | Output | Power Good | J1-148 | Active high when all on-module power supplies are working properly. |
JTAGEN | Input | JTAG Select | J2-131 | Low for normal operation. |
.. | .. | .. | .. | .. |
Table x: System Controller CPLD I/O pins.
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High-speed USB ULPI PHY
USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).
PHY Pin | Connected to | Notes |
---|---|---|
ULPI | PS bank MIO52 ... MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY |
REFCLK | - | 52MHz from on board oscillator (U9) |
REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) |
RESETB | SC CPLD U17 | Low active USB PHY Reset (pulled-up to PS_1.8V). |
DP, DM | 4-port USB3.0 Hub U4 | USB2.0 data lane |
CPEN | - | External USB power switch active-high enable signal |
VBUS | 5V | Connected to USB VBUS via a series of resistors, see schematic |
ID | - | For an A-device connect to the ground. For a B-device, leave floating |
Table 17: USB PHY interface connections
Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
4-port USB3.0 Hub
On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.
On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.
The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.
PHY Pin | Connected to | Notes |
---|---|---|
MDC/MDIO | PS bank MIO76, MIO77 | - |
PHY LED0..1 | SC CPLD U17, pin 67,86 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
PHY_LED2 / INTn: | SC CPLD U17, pin 85 | Active low interrupt line |
PHY_CLK125M | SC CPLD U17, pin 70 | 125 MHz Ethernet PHY clock out |
CONFIG | SC CPLD U17, pin 65 | Configuration of PHY address LSB and VDDO level |
RESETn | SC CPLD U17, pin 62 | Active low reset line |
RGMII | PS bank MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
SGMII | - | Serial Gigabit Media Independent Interface |
MDI | RJ45 GbE MagJack J7 | Media Dependent Interface |
Table 18: Ethernet PHY interface connections
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
8-Channel I²C Switches
All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.
For this purpose, the TEB0911 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.
Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.
The I2C bus works internally on-module with reference voltage 1.8V, it is connected to the MPSoC I2C interface via PS MIO bank (pins MIO38, MIO39) configured as master.
MIO | Signal Schematic Name | Notes |
---|---|---|
38 | I2C_SCL | 1.8V reference voltage |
39 | I2C_SDA | 1.8V reference voltage |
Table 19: MIO-pin assignment of the module's I2C interface
I2C addresses for on-board slave devices are listed in the table below:
I²C Slave Devices connected to MPSoC I²C Interface | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
---|---|---|---|
8-channel I²C switch U16 | - | 0x73 | I2C_SDA / I2C_SCL |
8-channel I²C switch U27 | - | 0x77 | I2C_SDA / I2C_SCL |
SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL) | - | User programmable | I2C_SDA / I2C_SCL |
I²C Slave Devices connected to 8-channel I²C Switch U16 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
On-board Quad programmable PLL clock generator U35 Si5338 | 0 | 0x70 | MCLK_SDA / MCLK_SCL |
8-bit I²C IO Expander U44 | 1 | 0x26 | SFP_SDA / SFP_SCL |
PCIe Connector J1 | 2 | module dependent | PCIE_SDA / PCIE_SCL |
SFP+ Connector J14A | 3 | module dependent | SFP1_SDA / SFP1_SCL |
SFP+ Connector J14B | 4 | module dependent | SFP2_SDA / SFP2_SCL |
Configuration EEPROM U24 | 5 | 0x54 | MEM_SDA / MEM_SCL |
Configuration EEPROM U36 | 5 | 0x52 | MEM_SDA / MEM_SCL |
Configuration EEPROM U41 | 5 | 0x51 | MEM_SDA / MEM_SCL |
Configuration EEPROM U22 | 5 | 0x50 | MEM_SDA / MEM_SCL |
8-bit I²C IO Expander U38 | 5 | 0x27 | MEM_SDA / MEM_SCL |
FMC Connector J5 | 6 | module dependent | FMC_SDA / FMC_SCL |
USB3.0 Hub configuration EEPROM U5 | 7 | 0x51 | USBH_SDA / USBH_SCL |
USB3.0 Hub | 7 | 0x60 | USBH_SDA / USBH_SCL |
I²C Slave Devices connected to 8-channel I²C Switch U27 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
PMOD Connector P1 | 0 | module dependent | PMOD_SDA / PMOD_SCL |
24-bit Audio Codec U3 | 1 | 0x38 | A_I2C_SDA / A_I2C_SCL |
FireFly Connector J15 | 2 | module dependent | FFA_SDA / FFA_SCL |
FireFly Connector J22 | 3 | module dependent | FFB_SDA / FFB_SCL |
On-module Quad programmable PLL clock generator Si5345 (TE0808) | 4 | 0x69 | PLL_SDA / PLL_SCL |
SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL) | 5 | User programmable | SC_SDA / SC_SCL |
8-bit I²C IO Expander U34 | 6 | 0x24 | FF_E_SDA / FF_E_SCL |
PMOD Connector P3 | 7 | module dependent | EXT_SDA / EXT_SCL |
Table 20: On-board peripherals' I2C-interfaces device slave addresses
Configuration EEPROMs
The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:
EEPROM Modell | Schematic Designator | Memory Density | Purpose |
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24LC128-I/ST | U24 | 128 Kbit | user |
24AA025E48T-I/OT | U36 | 2 Kbit | user |
24AA025E48T-I/OT | U41 | 2 Kbit | user |
24AA025E48T-I/OT | U42 | 2 Kbit | user |
24LC128-I/ST | U5 | 128 Kbit | USB3.0 Hub U4 configuration memory |
Table 21: On-board configuration EEPROMs overview
CAN FD Transceiver
On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.
The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.
eMMC Memory
The TEB0911 UltraRack board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit
Table x: Quad SPI interface signals and connections.
SD Card Interface
Describe SD Card interface shortly here if the module has one...
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Table x: SD Card interface signals and connections.
Ethernet Interface
On board Gigabit Ethernet PHY is provided with ...
Ethernet PHY connection
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Table x: ...
USB Interface
USB PHY is provided with ...
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Table x: ...
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:
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Table x: I2C slave device addresses.
On-board Peripherals
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System Controller CPLD
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed information, refer to the reference page of the SC CPLD firmware of this module.
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DDR Memory
By default TE0xxx module has ... DDRx SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
High-speed USB ULPI PHY
Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
RTC - Real Time Clock
An temperature compensated Intersil ISL...
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MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
Oscillators
The TEB0911 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
Clock Source | Schematic Name | Frequency | Clock Input Destination |
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SiTime SiT8008BI oscillator, U10 | USB0_RCLK | 52.000000 MHz | USB 2.0 transceiver PHY U9, pin 26 |
SiTime SiT8008BI oscillator, U13 | ETH_CLK | 25.000000 MHz | Gigabit Ethernet PHY U12, pin 34 |
SiTime SiT8008BI oscillator, U7 | - | 25.000000 MHz | Quad PLL clock generator U35, pin 3 |
DSC1123 oscillator, U23 | B505_CLK1 | 150.0000 MHz | PS GT Bank, dedicated for SATA interface |
DSC1123 oscillator, U6 optional, not equipped | B505_CLK0 | 100.0000 MHz | PS GT Bank, dedicated for USB interface |
Silicon Labs 570FBB000290DG, U45 optional, not equipped | B47_L5 (LVDS) | 250.MHz | PL Bank clock capable input pins |
SiTime SiT8008BI oscillator, U25 | CLK_CPLD | 25.576000 MHz | System Controller CPLD U35, pin 128 |
Table 16: Reference clock signal oscillators
Programmable Clock Generator Si5338A
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.
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Table : Programmable quad PLL clock generator inputs and outputs.
Programmable Clock Generator Si5345A
Oscillators
The module has following reference clock signals provided by on-board oscillators and external source from carrier board:
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LED | Color | Connected to | Description and Notes |
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D1 | Green | ||
.. | .. | .. | .. |
Table : On-board LEDs.
User Buttons
Configuration DIP-switches
Backup Battery Holder
Power and Power-On Sequence
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The maximum power consumption of a module the board mainly depends on the design running on the FPGA.
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Power Input | Typical Current | ||
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24V VIN | TBD* | 3.3VIN | TBD* |
Table : Typical power consumption. * TBD - To , *to Be Determined soon with reference design setup.
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Power supply with minimum current capability of ...A for system startup is recommended.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
?? A for system startup is recommended.
The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.
This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.
The Processing System contains three Power Domains:
- Battery Power Domain (BBRAM and RTC)
- Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
- Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
- Programmable Logic (PL)
Power Distribution Dependencies
There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:
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To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power Distribution Dependencies
Regulator dependencies and max. current.
Put power distribution diagram here...
Figure : Module power distribution diagram.
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/Os should be tri-stated during power-on sequence. |
Power-On Sequence
The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.
On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller CPLD U27:
- Low-Power Domain (LPD)
- Programmable Logic (PL) and Full-Power Domain (FPD)
- GTH, PS GTR transceiver and DDR memory
Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance is asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good)Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:Put power-on diagram here....
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Figure : Module power-on diagram.
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