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The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq Ultrascale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM socket with 64-bit wide data bus, 20 Gigabit transceivers 24 MGT Lanes and powerful switch-mode power supplies for all on-board voltages.. The motherboard exposes the Zynq MPSoC's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ MPSoC and for developing purposes. The motherboard is capable to be fitted to a dedicated enclosure. On the enclosure's rear and front panel, I/O's and MGT interfaces are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for USB3.0, SFP+, SSD, GbE, etc.
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The TEB0911 Ultrarack+ offers 6FMC 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes for use by other mezzanine modules and expansion cards.
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draw.io Diagram | ||||||||||||||||||||||||
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Figure x: General overview of the FMC HPC connectors
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TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
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FMC | Interfaces | Schematic Net Name | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
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J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | 3.3V | - | |
46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | |||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | ||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3V | |||
MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4 MGT Lanes | ||
Clock Input | - | 1 | Bank 128 GTH | - | Reference Clock Input to MGT Bank | ||
Control Signals | FMCA_PG_C2M | 1 | - | SC CPLD U27 Bank 0 | 3.3VSB | ||
FMCA_PG_M2C | 1 | - | SC CPLD U27 Bank 0 | 3.3VSB | |||
FMCA_PRSNT | 1 | - | SC CPLD U27 Bank 0 | 3.3VSB | |||
J21 | 20 | 10 | |||||
J4 | 92 | 46 | |||||
J8 | |||||||
J7 | |||||||
J6 |
Table MGT Lanes
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MGT lanes should be listed separately, as they are more specific than just general I/Os.
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
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