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Figure x: General overview of the FMC connectors
Following table shows an overview of the interfaces available on the FMC connectors:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||
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J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - | ||
46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |||
MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4x MGT lanes | |||
Clock Input | - | 1 | Bank 128 GTH | - | 1x Reference clock input to MGT bank | |||
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' | |||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||
J21 (FMC F) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - | ||
28 | 14 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||||
68 | 34 | SC CPLD U27 Bank 3 | FMCAF_1V8 | - | ||||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |||
MGT | - | 8 (4 x RX/TX) | Bank 129 GTH | - | 4x MGT lanes | |||
Clock Input | - | 1 | Bank 129 GTH | - | 1x Reference clock input to MGT bank | |||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT' | |||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||
J4 | I/O | 24 | 12 | Bank 47 HD | FMCBC_1V8 | - | ||
20 | 10 | Bank 48 HD | FMCBC_1V8 | - | ||||
24 | 12 | Bank 49 HD | FMCBC_1V8 | - | ||||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |||
JTAG | 4 | - | SC CPLD U27 Bank 0 | 3.3VSB | - | |||
MGT | - | 8 (4 x RX/TX) | Bank 130 GTH | - | 4x MGT lanes | |||
Clock Input | - | 2 | Bank 48 HD | - | 2x LVDS reference Reference clock inputs to PL bank | |||
- | 1 | Bank 130 GTH | - | 1x Reference clock input to MGT bank | ||||
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT' | |||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||
J8 | I/O | 20 | 10 | Bank 50 HD | FMCBC_1V8 | - | ||
68 | 34 | Bank 67 HP | FMCBC_1V8 | - | ||||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |||
MGT | - | 8 (4 x RX/TX) | Bank 230 GTH | - | 4x MGT lanes | |||
Clock Input | - | 2 | Bank 50 HD | - | 2x LVDS reference Reference clock inputs to PL bank | |||
- | 1 | Bank 230 GTH | - | 1x Reference clock input to MGT bank | ||||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT' | |||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||
J7 | I/O | 20 | 10 | Bank 65 HP | FMCDE_1V8 | - | ||
48 | 24 | Bank 66 HP | FMCDE_1V8 | - | ||||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |||
MGT | - | 8 (4 x RX/TX) | Bank 229 GTH | - | 4x MGT lanes | |||
Clock Input | - | 2 | Bank 65 HD65 HP | - | 2x LVDS reference Reference clock inputs to PL bank | |||
- | 1 | Bank 229 GTH | - | 1x Reference clock input to MGT bank | ||||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCCFMCD_PG_C2M', 'FMCCFMCD_PG_M2C', 'FMCCFMCD_PRSNT' | |||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||
J7 |
| ED) | I/O | 24 | 12 | Bank 65 HP | FMCDE_1V8 | - |
44 | 22 | Bank 64 HP | FMCDE_1V8 | - | ||||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |||
MGT | - | 8 (4 x RX/TX) | Bank 228 GTH | - | 4x MGT lanes | |||
Clock Input | - | 2 | Bank 64 HP | - | 2x Reference clock inputs to PL bank | |||
- | 1 | Bank 228 GTH | - | 1x Reference clock input to MGT bank | ||||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT' |
Table x: FMC connectors interfaces overview
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<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. --> |
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