Page History
...
draw.io Diagram | ||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Figure x: General overview of the FMC connectors
Following table shows an overview of the interfaces tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors:connectors A - F:
FMC A Connector
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4x MGT lanes | |
Clock Input | - | 1 | Bank 128 GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' |
Table 3: FMC A connector interfaces
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J10 (FMC A) | 0 | 128 | GTH |
|
|
|
1 | 128 | GTH |
|
|
| |
2 | 128 | GTH |
|
|
| |
3 | 128 | GTH |
|
|
|
Table 4: FMC A connector MGT lanes
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J10 (FMC A) |
| 128 |
|
| Supplied by attached module |
Table 5: FMC A connector clock signal input
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J10 (FMC A) | FMCA_3V3 |
| DCDC U32, | Enable by SC CPLD U27, Signal: 'EN_A_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF |
| DCDC U51, | - | |
FMCAF_1V8 |
| DCDC U39, | - |
Table 6: FMC A connector available VCC/VCCIO
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J10 (FMC A) | M1 | Enable by SC CPLD U27, Signal: 'FAN_A_EN' | - |
Table 7: FMC A connector cooling fan
FMC F Connector
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - | ||||||
46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||||||||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |||||||
JTAG | 4 | - | SC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | J21I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
28 | 14 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||||||||
68 | 34 | SC CPLD U27 Bank 3 | FMCAF_1V8 | - | ||||||||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |||||||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |||||||
MGT | - | 8 (4 x RX/TX) | Bank 129 GTH | - | 4x MGT lanes | |||||||
Clock Input | - | 1 | Bank 129 GTH | - | 1x Reference clock input to MGT bank | |||||||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT' | |||||||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||||||
J4 | I/O | 24 | 12 | Bank 47 HD | FMCBC_1V8 | - | ||||||
20 | 10 | Bank 48 HD | FMCBC_1V8 | - | ||||||||
24 | 12 | Bank 49 HD | FMCBC_1V8 | - | ||||||||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |||||||
JTAG | 4 | - | SC CPLD U27 Bank 0 | 3.3VSB | - | |||||||
MGT | - | 8 (4 x RX/TX) | Bank 130 GTH | - | 4x MGT lanes | |||||||
Clock Input | - | 2 | Bank 48 HD | - | 2x Reference clock inputs to PL bank | |||||||
- | 1 | Bank 130 GTH | - | 1x Reference clock input to MGT bank | ||||||||
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT' | |||||||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||||||
J8 | I/O | 20 | 10 | Bank 50 HD | FMCBC_1V8 | - | ||||||
68 | 34 | Bank 67 HP | FMCBC_1V8 | - | ||||||||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |||||||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |||||||
MGT | - | 8 (4 x RX/TX) | Bank 230 GTH | - | 4x MGT lanes | |||||||
Clock Input | - | 2 | Bank 50 HD | - | 2x Reference clock inputs to PL bank | |||||||
- | 1 | Bank 230 GTH | - | 1x Reference clock input to MGT bank | ||||||||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT' | |||||||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||||||
J7 | I/O | 20 | 10 | Bank 65 HP | FMCDE_1V8 | - | ||||||
48 | 24 | Bank 66 HP | FMCDE_1V8 | - | ||||||||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |||||||
JTAG | 4 | - | SCCPLD U27 Bank 2 | 3.3VSB | - | |||||||
MGT | - | 8 (4 x RX/TX) | Bank | 229128 GTH | - | 4x MGT lanes | ||||||
Clock Input | - | 2 | Bank 65 HP | - | 2x Reference clock inputs to PL bank- | 1 | Bank | 229128 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank | 20 | 3.3VSB | ' | FMCDFMCA_PG_C2M', ' | FMCDFMCA_PG_M2C', ' | FMCDFMCA_PRSNT' | |||
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | ||||||
J21J6 (FMC EF) | I/O | 24 | 12 | Bank 65 HP | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - | |||
28 | 14 | SC CPLD U27 Bank 1 | FMCAFFMCDE_1V8 | -44 | ||||||||
68 | 2234 | SC CPLD U27 Bank | 64 HP3 | FMCDEFMCAF_1V8 | - | |||||||
I²C | 2 | - | I²C-Switch U13U37 | - | Muxed to MIO Bank 501 I²C Inteface | |||||||
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |||||||
MGT | - | 8 (4 x RX/TX) | Bank 228 129 GTH | - | 4x MGT lanes | |||||||
Clock Input | - | 2 | Bank 64 HP | - | 2x Reference clock inputs to PL bank | - | 1 | Bank 228 129 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCEFMCF_PG_C2M', 'FMCEFMCF_PG_M2C', 'FMCEFMCF_PRSNT' |
Table x: FMC connectors interfaces overview
HTML |
---|
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
--> |
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin and FPGA pins:
...
- MGT_RX0_P
- MGT_RX0_N
- MGT_TX0_P
- MGT_TX0_N
...
- JM3-8
- JM3-10
- JM3-7
- JM3-9
...
- MGTHRXP0_225, Y2
- MGTHRXN0_225, Y1
- MGTHTXP0_225, AA4
- MGTHTXN0_225, AA3
...
- MGT_RX1_P
- MGT_RX1_N
- MGT_TX1_P
- MGT_TX1_N
...
- JM3-14
- JM3-16
- JM3-13
- JM3-15
...
- MGTHRXP1_225, V2
- MGTHRXN1_225, V1
- MGTHTXP1_225, W4
- MGTHTXN1_225, W3
...
- MGT_RX4_P
- MGT_RX4_N
- MGT_TX4_P
- MGT_TX4_N
...
- JM1-12
- JM1-10
- JM1-6
- JM1-4
...
- MGTHRXP0_224, AH2
- MGTHRXN0_224, AH1
- MGTHTXP0_224, AG4
- MGTHTXN0_224, AG3
...
- MGT_RX5_P
- MGT_RX5_N
- MGT_TX5_P
- MGT_TX5_N
...
- JM1-24
- JM1-22
- JM1-18
- JM1-16
...
- MGTHRXP1_224, AF2
- MGTHRXN1_224, AF1
- MGTHTXP1_224, AF6
- MGTHTXN1_224, AF5
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J4 | I/O | 24 | 12 | Bank 47 HD | FMCBC_1V8 | - |
20 | 10 | Bank 48 HD | FMCBC_1V8 | - | ||
24 | 12 | Bank 49 HD | FMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 0 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 130 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 48 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 130 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT' | |
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
J8 | I/O | 20 | 10 | Bank 50 HD | FMCBC_1V8 | - |
68 | 34 | Bank 67 HP | FMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 230 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 50 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 230 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT' | |
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
J7 | I/O | 20 | 10 | Bank 65 HP | FMCDE_1V8 | - |
48 | 24 | Bank 66 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 229 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 65 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 229 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT' | |
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
J6 | I/O | 24 | 12 | Bank 65 HP | FMCDE_1V8 | - |
44 | 22 | Bank 64 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 228 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 64 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 228 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT' |
Table x: FMC connectors interfaces overview
HTML |
---|
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
--> |
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin and FPGA pins:
...
Table x: MGT lanes
Below are listed MGT banks reference clock sources.
...