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Figure x: General overview of the FMC connectors
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Connector | Interface | Signal Schematic Name | XMOD Header Pin | Connected to | VCCIO | VCC |
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XMOD Header J24 | JTAG | F_TCK | J24-4 | Bank 503 PS Config, Pin R25 | PS_1V8 | 3V3SB |
F_TDI | J24-10 | Bank 503 PS Config, Pin U25 | ||||
F_TDO | J24-8 | Bank 503 PS Config, Pin T25 | ||||
F_TMS | J24-12 | Bank 503 PS Config, Pin R24 | ||||
GPIO/ | XMOD2_A | J24-3 | SC CPLD Bank U27, bank 5, Pin K7 | |||
XMOD2_B | J24-7 | SC CPLD Bank U27, bank 5, Pin K6 | ||||
XMOD2_E | J24-9 | SC CPLD Bank U27, bank 5, Pin H7 | ||||
XMOD2_G | J24-11 | SC CPLD Bank U27, bank 5, Pin H6 | ||||
XMOD Header J35 | JTAG | C_TCK | J35-4 | SC CPLD Bank U27, bank 0, Pin A8 | 3V3SB | |
C_TDI | J35-10 | SC CPLD Bank U27, bank 0, Pin C7 | ||||
C_TDO | J35-8 | SC CPLD Bank U27, bank 0, Pin A6 | ||||
C_TMS | J35-12 | SC CPLD Bank U27, bank 0, Pin C9 | ||||
GPIO/ | XMOD1_A | J35-3 | SC CPLD Bank U27, bank 0, Pin B19 | |||
XMOD1_B | J35-9 | SC CPLD Bank U27, bank 0, Pin A17 | ||||
XMOD1_E | J35-7 | SC CPLD Bank U27, bank 0, Pin C17 | ||||
XMOD1_G | J35-11 | SC CPLD Bank U27, bank 0, Pin A18 |
Table 33: XMOD interface signals
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PHY Pin | Connected to | Notes |
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MDC/MDIO | PS bank 502 MIO76, MIO77 | - |
PHY LED0..2 | SC CPLD Bank U27, bank 4, pin L5, L1, K1 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
PHY_CLK125M | SC CPLD Bank U27, bank 4, pin K2 | 125 MHz Ethernet PHY clock out |
CONFIG | pulled up to PS_1V8 | Configuration of PHY address LSB and VDDO level |
RESETn | SC CPLD Bank U27, bank 4, pin L6 | Active low reset line |
RGMII | PS bank 502 MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
SGMII | - | Serial Gigabit Media Independent Interface |
MDI | RJ45 GbE MagJack J13 | Media Dependent Interface |
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IC | Interface | Signal Schematic Names | Connected to | Note |
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USB3 Hub U4 | USB3 Upstream MGT lane | B505_TX1_N, B505_RX1_N, | PS GTR bank 505 Pins: PS_MGTRRXP1_505, AA31, | - |
USB2 Uptream data LVDS pair | USB0_D_P, USB0_D_N | USB2 PHY U15 Pins: 18,19 | - | |
USB3 Downstream lane | USB3_RXDN1_D_P, USB3_TXDN1_D_P, USB3_RXDN2_D_P, USB3_TXDN2_D_P, | 2-port USB3 A / RJ-45 connector | - | |
USB2 Downstream LVDS pair | USB2_DN1_D_P, USB2_DN2_D_P, | 2-port USB3 A / RJ-45 connector | - | |
I²C | USBH_SDA, USBH_SCL | Configuration EEPROM U5, 8-channel I²C-switch U37 | EEPROM U5 is configuration and parameter memory of USB3 hub U4. | |
Control Lines | USBH_MODE0, USBH_MODE1, USBH_RST | SC CPLD U27, Bank bank 2 Pins: Y17, Y16, Y15 | - | |
USB2 PHY U15 | USB2 ULPI | USB0_STP, | PS bank 502 Pins: MIO52 ... MIO63 | - |
USB2 data LVDS pair | USB0_D_P, | USB3 Hub U4 Pins: 71,72 | - | |
Control Lines | USB0_RST | SC CPLD U27, Bank bank 4 PinsPin: M2 | - |
Table 36: USB3 interface signals ans and interfaces
SFP+ Interface
The TEB0911 board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) with data transmission rates up to 10 Gbit/s.
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Figure X: SFP+ Interface
Connector | Interface | Signal Schematic Name | Connected to | FPGA Direction | Description | Logic | Notes | |||||||||||||||||||
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SFP+ | ConnectorJ9A | MGT Lane | B129_TX3_ | NP, | PN B129_RX3_ | NP, | PPS_1V8 | XMOD2_B | SC CPLD Bank 5, Pin K6 | XMOD2_E | SC CPLD Bank 5, Pin H7 | XMOD2_G | SC CPLD Bank 5, Pin H6 | I²C | Control Lines | SFP+ Connector J9B | MGT Lane | 3V3SB | XMOD1_B | SC CPLD Bank 0, Pin A17 | XMOD1_E | SC CPLD Bank 0, Pin C17 | XMOD1_G | SC CPLD Bank 0, Pin A18 | I²C | Control Lines |
Signal Schematic Name | Connector Type | FPGA Direction | Description | Logic | ||||||||||||||||||||||
SFPx_TX_DISABLE | SFP+ | Output | SFP Enabled / Disabled | Low active | ||||||||||||||||||||||
SFPx_LOS | SFP+ | Input | Loss of receiver signal | High active | SFPx_RS0 | SFP+|||||||||||||||||||||
N | GTH bank 129 Pins: MGTHRXP3_129, F33, | BiDir | Multi gigabit highspeed data lane | - | - | |||||||||||||||||||||
I²C | SFP0_SDA, SFP0_SCL | 8-channel I²C-switch U37 | BiDir | 2-wire Serial Interface | - | - | ||||||||||||||||||||
Control Lines | SFP0_RS0 | I²C 8-bit I/O Port-Expander U86 | Output | Full RX bandwidth | Low active | I/O Port Expander on | ||||||||||||||||||||
SFP0_RS1 | Output | Reduced RX bandwidth | Low active | |||||||||||||||||||||||
SFP0_M-DEF0 | Input | Module present / not present | Low active | |||||||||||||||||||||||
SFP0_TX_FAULT | Input | Fault / Normal Operation | High active | |||||||||||||||||||||||
SFP0_LOS | SC CPLD U27, bank 2, pin V8 | Input | Loss of receiver signal | High active | - | |||||||||||||||||||||
SFP0_TX_DIS | SC CPLD U27, bank 2, pin Y7 | Output | SFP Enabled / Disabled | Low active | - | |||||||||||||||||||||
SFP+ J9B | MGT Lane | B129_TX2_P, B129_RX2_P, | GTH bank 129 Pins: MGTHRXP2_129, H33, | BiDir | Multi gigabit highspeed | - | - | |||||||||||||||||||
I²C | SFP1_SDA, | 8-channel I²C-switch U37 | BiDir | 2-wire Serial Interface | - | - | ||||||||||||||||||||
Control Lines | SFP1_RS0 | I²C 8-bit I/O Port-Expander U86 | Output | Full RX bandwidth | Low active | I/O Port Expander on | ||||||||||||||||||||
SFP1_RS1 | Output | Reduced RX bandwidth | Low active | |||||||||||||||||||||||
SFP1_M-DEF0 | Input | Module present / not present | Low active | |||||||||||||||||||||||
SFP1_TX_FAULT | Input | Fault / Normal Operation | High active | |||||||||||||||||||||||
SFP1_LOS | SC CPLD U27, bank 2, pin W7 | Input | Loss of receiver signal | High active | - | |||||||||||||||||||||
SFP1_TX_DIS | SC CPLD U27, bank 2, pin V7 | Output | SFP Enabled / Disabled | Low active | - |
Table 37: SFP+ interface signals and interfaces
SSD Interface
On the TEB0911 UltraRack board one SSD interface is available provided by an NGFF (Next Generation Form Faktor) M.2 socket (Key M) which supports data transmission rates of PCIe3, SATA3 and USB3 interfaces.
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Figure X: SSD Interface
Connector | Interface | Signal Schematic Name | Connected to | FPGA Direction | Description | Logic | |
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SFP+ J9A | MGT Lane | B129_TX3_P, B129_RX3_P, | GTH bank 129 Pins: MGTHRXP3_129, F33, | BiDir | Multi gigabit highspeed data lane | - | |
I²C | SFP0_SDA, SFP0_SCL | 8-channel I²C-switch U37 | BiDir | 2-wire Serial Interface | - | ||
Control Lines | SFP0_RS0 | I²C 8-bit I/O Port-Expander U86 | Output | Full RX bandwidth | Low active |
SFP0_RS1 |
Output | Reduced RX bandwidth | Low active |
SFP0_M-DEF0 |
Input | Module present / not present | Low active |
SFP0_TX_FAULT |
Input | Fault / Normal Operation | High active |
SFP0_ |
SSD Interface
LOS | SC CPLD U27, bank 2, pin V8 | Input | Loss of receiver signal | High active | |
SFP0_TX_DIS | SC CPLD U27, bank 2, pin Y7 | Output | SFP Enabled / Disabled | Low active |
DisplayPort Interface
DDR4 Memory Socket
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Figure : Module power-on diagram.
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