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Connector | Interface | Signal Schematic Name | Connected to | Notes |
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M.2-NGFF PCIe Socket U2 | MGT Lane |
| PS_MGTRTXP0_505, AB29 | Multi gigabit highspeed TX: Output RX: Input |
Clock Input |
| Quad programmable PLL clock generator U12, CLK0 | Reference clock signal | |
Control Lines |
| SC CPLD U27, bank 2, pin AA13 | LED, Output, High active | |
| SC CPLD U27, bank 2, pin AA12 | PCIe sleep state, Input, Low active | ||
| SC CPLD U27, bank 2, pin AA11 | PCIe reset input, Input, Low active | ||
| SC CPLD U27, bank 2, pin AB11 | PCIe Link reactivation, Input, Low active | ||
| connect to GND | PCIe Clock Request, Low active |
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