Page History

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Design supports following carriers:

Carrier Model	Notes	TE0701	TE0703
TE0705	TE0706	TEBA0841	used as reference carrier

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Additional Hardware	Notes
USB Cable for JTAG/UART	Check Carrier Board and Programmer for correct type
XMOD Programmer	Carrier Board dependent, only if carrier has no own FTDI
Heat sink	It's recommended to use heat sink for this design

Content

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Reference Design is available on:

TE0841 "Test BoardIBERT" Reference Design

Design Flow

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Connect JTAG and power on PCB
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

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Connect JTAG and power on PCB
Open Vivado HW Manager
Program FPGA with Bitfile from "prebuilt\hardware\<short dir>"Note SREC Bootloader try to find application on flash, this will stop, if Flash is empty.

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)

Power on PCB
Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts MicroBlaze, MicroBlaze SREC Bootloader loads Hello TE0781 from Flash into RAM and starts application. Example will be run on UART consoleIBERT.
Do not reboot, if Bitfile programming over JTAG is used as programming method.

UART

Open Serial Console (e.g. putty)

Speed: 9600
COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

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1. On TE0841 SI5338 has default configuration and reprogramming of SI5338 is optional
LED:
1. D1 (green) OFF→ MCS SI configuration finished (System Reset is off)

Vivado HW Manager:

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
1. Set radix from VIO signals (fm_si...) to unsigned integer.
  Note: Frequency Counter is inaccurate and displayed unit is Hz
2. SI will be configured with MCS firmware, default all off on PCB REV01
3. LED control via VIO
4. MGT CLK Freq can be changed over BUFG_GT control signals divider
5. MCS Reset possible via VIO

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System Design - Vivado

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Block Design

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Constrains

Basic module constrains

Manager
"Refresh device" is needed after Bitfile programming, because MCS reconfigure SI5338 and enables IBERT a little bit later.
1. loopback depends on TEB0841 Revision an connection

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IBERT	Component Name	Net Name	TEB0841
X0Y0	224-0	MGT4	loop back RX/TX
X0Y1	224-1	MGT5	loop back RX/TX
X0Y2	224-2	MGT6	loopback over SD Pin header possible with lower Linerate otherwise use internal loopback
X0Y3	224-3	MGT7	loop back RX/TX. Note: N.C. on TEB0841-01, use internal loopback
X0Y4	225-0	MGT0	loop back RX/TX
X0Y5	225-1	MGT1	loop back RX/TX
X0Y6	225-2	MGT2	loop back RX/TX
X0Y7	225-3	MGT3	loopback over sfp possible

System Design - Vivado

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Block Design

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HDL

IBERT_top.v
ibert xci IPs

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

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Code Block

language	ruby
title	ibert_iultrascale_gth_ddr40.xdc
linenumbers	true

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]
create_clock -name ddr4_0_clk -period 4.95 [get_pins */ddr4_0/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
create_clock -name ddr4_1_clk -period 4.95 [get_pins */ddr4_1/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design

Code Block

language	ruby
title	_i_qspi.xdc
linenumbers	true

# You must provide all the delay numbers
# CCLK delay is 0.1, 6.7 ns min/max for ultra-scale devices; refer Data sheet
# Consider the max delay for worst case analysis
set cclk_delay 6.7
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay] [get_pins -hierarchical *USRCCLKO]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1
# Max delay constraints are used to instruct the tool to place IP near to STARTUPE3 primitive.
# If needed adjust the delays appropriately
set_max_delay -datapath_only -from [get_pins -hier {*STARTUP*_inst/DI[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/USRCCLKO] 1.000
#set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*] {*STARTUP*_inst/DTS[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*]] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DTS[*]] 1.000

Code Block

language	ruby
title	_i_fm.xdc
linenumbers	true

set_false_path -from [get_clocks {msys_i/util_ds_buf_5/U0/BUFG_GT_O[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks {msys_i/util_ds_buf_6/U0/BUFG_GT_O[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_6/U0/BUFG_GT_O[0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_5/U0/BUFG_GT_O[0]}]

set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_4/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks {msys_i/util_ds_buf_4/U0/IBUF_OUT[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
# file: ibert_ultrascale_gth_0.xdc
####################################################################################
##   ____  ____ 
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 2012.3
##  \   \         Application : IBERT Ultrascale
##  /   /         Filename : example_ibert_ultrascale_gth_0.xdc
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## 
## Generated by Xilinx IBERT 7Series 
##**************************************************************************
##
## Icon Constraints
##
create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i]
set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous
set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]

##gth_refclk lock constraints
##
set_property PACKAGE_PIN AD6 [get_ports gth_refclk0p_i[0]]
set_property PACKAGE_PIN AD5 [get_ports gth_refclk0n_i[0]]
set_property PACKAGE_PIN AB6 [get_ports gth_refclk1p_i[0]]
set_property PACKAGE_PIN AB5 [get_ports gth_refclk1n_i[0]]
##
## Refclk constraints
##
create_clock -name gth_refclk0_0 -period 8.0 [get_ports gth_refclk0p_i[0]]
create_clock -name gth_refclk1_0 -period 8.0 [get_ports gth_refclk1p_i[0]]
set_clock_groups -group [get_clocks gth_refclk0_0 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_0 -include_generated_clocks] -asynchronous
##
## System clock pin locs and timing constraints
##
set_property PACKAGE_PIN R25 [get_ports gth_sysclkp_i]
set_property IOSTANDARD LVDS [get_ports gth_sysclkp_i]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

SCU

MCS Firmware to configure SI5338 and Reset System.

Template location: \sw_lib\sw_apps\scu

Hello TE0841

Xilinx Hello World example as endless loop

Template location: \sw_lib\sw_apps\hello_te0841

SREC SPI Bootloader

SDK Projects

Application

SCU

MCS Firmware to configure SI5338 and Reset System.Modified Xilinx SREC Bootloader. Changes: Correct flash typ and SRec Start address, some additional console outputs, see source code

Template location: \sw_lib\sw_apps\srec_spi_bootloader \sw_lib\sw_services\xilisf_v5_9scu

Additional Software

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Trenz Electronic Documentation

Versions Compared

Old Version 1

New Version 2

Key

Content

Design Flow

Usage

UART

Vivado HW Manager:

System Design - Vivado

Block Design

Constrains

Basic module constrains

System Design - Vivado

Block Design

HDL

Constrains

Basic module constrains

Software Design - SDK/HSI

Application

SCU

Hello TE0841

SREC SPI Bootloader

Application

SCU

Additional Software