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- RGPIO CLK is FPGA_CPLD1 (up to 50MHz).
- Output is FPGA_CPLD2
- Input is FPGA_CPLD3
| RGPIO from FPGA | ValueDescription |
|---|---|
| 0...19 | Connected to EXT_IO(even numbers), if RGPIO is activated. , otherwise EXTIO is high impedance |
| 20...23 | Connected to RGPIO in 20...23, if RGPIO is activated. |
| 24...27 | reservedReserved |
| 28...31 | activation Activation code from FPGA. Must match "1010" |
| RGPIO to FPGA | Description |
|---|---|
| 0...19 | Connected to EXT_IO(odd numbers) |
| 20...23 | RGPIO out 20...23 from FPGA, if RGPIO is activated, otherwise zero |
| 24...27 | reservedReserved |
| 28...31 | activation Activation code from to FPGA. Must match "1010" |
LED
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| REV01 | REV01 |
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| 2018-05-28 | v.1 | REV01 | REV01 |
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| All |
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