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The Trenz Electronic TEI0001 is a low cost small-sized FPGA module integrating a Intel Cyclone 10LP 10CL025 MAX 10 FPGA SoC, 2 8 MByte serial memory for configuration and operation, 8 MByte SDRAM and a 3-axis accelerometer.

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title	Figure 1: TEI0003-02 block diagram

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Main Components

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title	Figure 2: TEI0003-02 FPGA module

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Intel MAX10 MAX 10 10M08 FPGA SoC, U1
8 Mbyte SDRAM 166MHz, U2
8 Mbyte QSPI Flash memory, U5
ST Microelectronics LIS3DH 3-axis accelerometer, U4
FTDI USB2 to JTAG/UART adapter, U3
Configuration EEPROM for FTDI chip, U9
12.0000 MHz oscillator, U7
8x red user LEDs, D2 ... D9
Red LED (Conf. DONE), D10
Green LED (indicating supply voltage), D1
Push button (user), S2
Push button (reset), S1
Micro USB2 B socket (receptacle), J9
1x14 pin header (2.54mm pitch), J2
1x6 pin header (2.54mm pitch), J4
2x6 Pmod connector, J6
3-pin header (2.54mm pitch), J3
1x14 pin header (2.54mm pitch), J1

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Table 1: Initial delivery state of programmable devices on the module

Boot Process

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power offBy default the configuration mode pins of the FPGA are set to load the FPGA design from the serial configuration memory, hence the FPGA is configured from serial configuration memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the serial configuration memory.

Signals, Interfaces and Pins

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6 low active Reset input

Bank	Connector Designator	I/O Signal Count	Bank Voltage	Notes
2	J2J1	9 4 I/O's	3.3V	-
2	J6	8 2 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same bank or pins can be shared	3.3V	Pmod connector
54	J1	8 2 I/O's	3.3V	-
54	J3J2	2 9 I/O's	3.3V	3.3V	-	5	J1	2 I/O's	3.3V	-	6	J6	8 I/O's	of bank 5 can be pulled-up to 3.3V (4K7 resistors)
1A	J1	7 analog inputs or GPIO	Pmod Connector	1	J4	4 I/O's	3.3V	JTAG interface	J2	1 Input	3.3V	Analog reference voltage (AREF) on pin J1-1
1A	J3	1 analog inputs or GPIO, 1 dedicated analog input	1 pin of bank 1A is dedicated analog input (AIN), other are also GPIO's as alternative function	1			3.3V
1B	J4	JTAG interface (4 I/O's)	3.3V	JTAG enable signal (JTAGEN) on pin J4-2, leave floating when using JTAG interface

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

3.3V

BankVCCIO	I/O's Count	Connected to	Notes
2	4	1	3.3V	6	LIS3DH digital motion sensor, U4	SPI interface, 2 interrupt lines
	48			1x6 pin header, J4	JTAG interface
	4			2 MByte serial configuration memory, U5	FPGA configuration memory with active serial (AS) x1 interface
	1			J2-10, push button S1	low active reset input	2	input
5	9	1x14 pin header, J2	GPIOs (2 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same Bank or pins can be shared)
1A	8	LEDs D2 ... D9	8 x red user LEDs
	8	FTDI FT2232H JTAG/UART Adapter, U3	configurable as GPIO/UART or other serial interfaces
	1	push button S2	user button
1B	10	pin headers J1, J3	GPIOs
5	6	pin headers J1	GPIOs
6	8	Pmod connector J6	GPIOs
6	1	Red LED, D10	Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7	19	8 Mbyte SDRAM 166MHz, U2	16bit SD-RAM memory interface
8	21	8 Mbyte SDRAM 166MHz, U2	16bit SD-RAM memory interface

Table 3: General overview of FPGA I/O banks

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Bank	I/O's Count	Connected to	Notes
2	4	1x14 pin header, J1	-
	8	Pmod connector, J6	-
	1	clock oscillator, U7	12.0000 MHz reference clock input
	1	optional clock oscillator, U6	footprints available for Microchip MEMS oscillator
5	9	1x14 pin header, J2

GPIOs (

2 I/O's (D11, D12) of bank

2

5 can be pulled-up to 3.3V (4K7 resistors) with

2

1 I/O

's of same Bank or pins can be shared)33.3V8LEDs D2 ... D98 x red user LEDs8FTDI FT2232H JTAG/UART Adapter, U3configurable as GPIO/UART or other serial interfaces1push button S2user button43.3V10

(D12_R) of same Bank and 1 I/O (D11_R) of bank 6
6	18	8 Mbyte SDRAM 166MHz, U2	16bit SD-RAM memory interface
3	22	pin headers J1, J3	GPIOs
5

3.3V

	6	pin headers J1	GPIOs
6

3.3V

	8	Pmod connector J6	GPIOs
	1	Red LED, D10	Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7

3.3V

19

8 Mbyte SDRAM 166MHz, U2

16bit SD-RAM memory interface

8

3.3V

8

21

8 Mbyte SDRAM 166MHz, U2

16bit SD-RAM memory interface

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JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3.

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JTAG Signal	Pin on Header J4	Note
TCK	3	-
TDI	5	-
TDO	4	-
TMS	6	-
JTAGEN	5	-

Table 4: optional JTAG pin header

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On-board serial configuration memory (U5) is provided by Intel EPCQ16ASI8N Winbond W74M64FVSSIQ with 16 64 MBit (2 8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 SPI interface.

Serial Memory U5 Pin	Signal Schematic Name	Connected to	Notes
Pin 2, DATA1	AS_DATA0	FPGA bank 1, pin H2	Data out
Pin 5, DATA0	AS_ASDO	FPGA bank 1, pin C1	Data in
Pin 1, nCS	AS_NCS	FPGA bank 1, pin D2	chip select
Pin 6, DCLK	AS_DCLK	FPGA bank 1, pin H1	clock

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title	Figure 3: Power Distribution Diagram

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FPGA	Design	Typical Power, 25C ambient
Intel Cyclone 10LP 10CL025 MAX 10 10M08 FPGA SoC	Not configured	TBD*

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Parameter	Min	Max	Units	Reference document
VIN supply voltage (5.0V nominal)	-0.3	6.0	V	EP53A7HQI / EP53A7LQI datasheet
I/O Input voltage for FPGA I/O bank	-0.5	4.2	V	Intel Cyclone MAX 10 LP datasheet
Storage Temperature	-40	+90	°C	LED R6C-AL1M2VY/3T datasheet

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Parameter	Min	Max	Units	Reference document
VIN supply voltage (5.0V nominal)	4.75	5.25	V	same as USB-VBUS specification
I/O Input voltage for FPGA I/O bank	–0.5	3.6	V	Intel Cyclone MAX 10 LP datasheet
Operating temperature range	0	+70	°C	Winbond datasheet W9864G6GT

Table 16: Recommended operating conditions

Note
Please check Intel MAX10 MAX 10 datasheet for complete list of absolute maximum and recommended operating ratings for the FPGA device.

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Trenz Electronic Documentation

Versions Compared

Old Version 6

New Version 7

Key

Main Components

Boot Process

Signals, Interfaces and Pins

FPGA I/O banks

JTAG Interface