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Table 3: General overview of FPGA I/O banks




BankI/O's CountConnected toNotes
241x14 pin header, J1-
8Pmod connector, J6-
1clock oscillator, U712.0000 MHz reference clock input
1optional clock oscillator, U6footprints available for Microchip MEMS oscillator
591x14 pin header, J22 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6
6188 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
3228 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
6LIS3DH 3-axis accelerometer, U44 I/O's for SPI interface, 2 interrupt lines
1A71x14 pin headers J1
, J3GPIOs56
7 analog inputs or GPIO's, 1 pin analog reference voltage input

2pin headers J1
GPIOs

68Pmod connector J6GPIOs
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7198 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
8218 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface


JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

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