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The Trenz Electronic TEI0001 MAX1000 is a low cost small-sized FPGA module integrating a Intel MAX 10 FPGA SoC, 8 MByte serial memory for configuration and operation, 8 MByte SDRAM and a 3-axis accelerometer.

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Intel MAX 10 10M08 FPGA SoC, U1
8 Mbyte SDRAM 166MHz, U2
8 Mbyte QSPI SPI Flash memory, U5
ST Microelectronics LIS3DH 3-axis accelerometer, U4
FTDI USB2 to JTAG/UART adapter, U3
Configuration EEPROM for FTDI chip, U9
12.0000 MHz oscillator, U7
8x red user LEDs, D2 ... D9
Red LED (Conf. DONE), D10
Green LED (indicating supply voltage), D1
Push button (user), S2
Push button (reset), S1
Micro USB2 B socket (receptacle), J9
1x14 pin header (2.54mm pitch), J2
1x6 pin header (2.54mm pitch), J4
2x6 Pmod connector, J6
3-pin header (2.54mm pitch), J3
1x14 pin header (2.54mm pitch), J1

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Storage device name	Content	Notes
Quad SPI Flash, U5	DEMO Design	-
I²C Configuration EEPROM, U9	Programmed	-

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on pin J1-11 pin of bank 1A is (AIN), other are also GPIO's as alternative function

Bank	Connector Designator	I/O Signal Count	Bank Voltage	Notes
2	J1	4 I/O's	3.3V	-
2	J6	8 I/O's	3.3V	Pmod connector
5	J1	2 I/O's	3.3V	-
5	J2	9 I/O's	3.3V	2 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors)
1A	J1	7 7x analog inputs or GPIO's	3.3V	, 1x Analog reference voltage (AREF)	3.3V	analog pins usable as GPIO's as alternative function
1A	J3	1 1x analog inputs or GPIO, 1 dedicated analog input	3.3V	1x dedicated analog input	3.3V	analog pins usable as GPIO's as alternative function
1B	J4	JTAG interface and 'JTAGEN' signal (4 5 I/O's)	3.3V	JTAG enable signal (JTAGEN) on pin J4-2, leave floating when using JTAG interfaceswitch between user I/O pins and JTAG pin functions

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

Bank	I/O's Count	Connected to	Notes
2	4	LIS3DH digital motion sensor, U4	SPI interface, 2 interrupt lines
	8	1x6 pin header, J4	JTAG interface
	4	2 MByte serial configuration memory, U5	FPGA configuration memory with active serial (AS) x1 interface
	1x14 pin header, J1	user GPIO's
8	Pmod connector, J6	user GPIO's
1	clock oscillator, U7	12.0000 MHz reference clock input
1	optional clock oscillator, U6	oscillator not fitted, footprints available for Microchip MEMS oscillator	1	J2-10, push button S1	low active reset input
5	9	1x14 pin header, J2	GPIOs (2 I/O's (D11, D12) of bank 2 5 can be pulled-up to 3.3V (4K7 resistors) with 2 1 I/O 's (D12_R) of same Bank or pins can be shared)
1A	8	LEDs D2 ... D9	8 x red user LEDs
	8	FTDI FT2232H JTAG/UART Adapter, U3	configurable as GPIO/UART or other serial interfaces
	1	push button S2	user button
1B	10	pin headers J1, J3	GPIOs
5	6	pin headers J1	GPIOs
6	8	Pmod connector J6	GPIOs
6	1	Red LED, D10	Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7	19	8 Mbyte SDRAM 166MHz, U2	16bit SD-RAM memory interface
8	21	8 Mbyte SDRAM 166MHz, U2	16bit SD-RAM memory interface

Table 3: General overview of FPGA I/O banks

16bit SD-RAM memory interface

	Bank	I/O's Count	Connected to	Notes
and 1 I/O (D11_R) of bank 6
6	18	8 MByte SDRAM 166MHz, U2	16bit SDRAM memory interface
3	22	8 MByte SDRAM 166MHz, U2	16bit SDRAM memory interface
3	6	LIS3DH 3-axis accelerometer, U4	4 I/O's for SPI interface, 2 interrupt lines
1A	8	1x14 pin headers J1	7 analog inputs or GPIO's, 1 pin analog reference voltage input
1A	2	pin headers J1	1 analog inputs or GPIO, 1 dedicated analog input
1B	5	pin header J4	4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
8	8	LEDs D2 ... D9	Red user LEDs
	6	SPI Flash memory, U5	4 pins SPI interface, 2 control lines
	6	FTDI FT2232H JTAG/UART Adapter, U3	6 pins configurable as GPIO/UART or other serial interfaces
	2	4	1x14 pin header, J1	-
		8	Pmod connector, J6	-
1		clock oscillator, U7	12.0000 MHz reference clock input
1		optional clock oscillator, U6	footprints available for Microchip MEMS oscillator
5	9	1x14 pin header, J2	2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6
6	18	8 Mbyte SDRAM 166MHz, U2	16bit SD-RAM memory interface
3	22	8 Mbyte SDRAM 166MHz, U2	16bit SD-RAM memory interface
3	6	LIS3DH 3-axis accelerometer, U4	4 I/O's for SPI interface, 2 interrupt lines
1A	7	1x14 pin headers J1	7 analog inputs or GPIO's, 1 pin analog reference voltage input
2	pin headers J1	6	8	Pmod connector J6	GPIOs
1	Red LED, D10	6	Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7	19	8 Mbyte SDRAM 166MHz, U2	16bit SD-RAM memory interface
8	21	8 Mbyte SDRAM 166MHz, U2

1	User button S2	user configurable
1	Reset button S1 and pin J2-10	low active reset line for FPGA reconfiguration

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3.

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JTAG Signal	Pin on Header J4	Note
TCK	3	-
TDI	5	-
TDO	4	-
TMS	6	-
JTAGEN	52	-

Table 4: optional JTAG pin header

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Serial Memory U5 Pin	Signal Schematic Name	Connected to	Notes
Pin 2, DATA1	AS_DATA0	FPGA bank 1, pin H2	Data out
Pin 5, DATA0	AS_ASDO	FPGA bank 1, pin C1	Data in
Pin 1, nCS	AS_NCS	FPGA bank 1, pin D2	chip select
Pin 6, DCLK	AS_DCLK	FPGA bank 1, pin H1	clock
Pin 6, DCLK

Table 5: Serial configuration memory interface connections

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Trenz Electronic Documentation

Versions Compared

Old Version 8

New Version 9

Key

FPGA I/O banks

JTAG Interface