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The Trenz Electronic TEI0001 MAX1000 is a low cost small-sized FPGA module integrating a Intel MAX 10 FPGA SoC, 8 MByte serial memory for configuration and operation, 8 MByte SDRAM and a 3-axis accelerometer.

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  1. Intel MAX 10 10M08 FPGA SoC, U1
  2. 8 Mbyte SDRAM 166MHz, U2
  3. 8 Mbyte QSPI SPI Flash memory, U5
  4. ST Microelectronics LIS3DH 3-axis accelerometer, U4
  5. FTDI USB2 to JTAG/UART adapter, U3
  6. Configuration EEPROM for FTDI chip, U9
  7. 12.0000 MHz oscillator, U7
  8. 8x red user LEDs, D2 ... D9
  9. Red LED (Conf. DONE), D10
  10. Green LED (indicating supply voltage), D1
  11. Push button (user), S2
  12. Push button (reset), S1
  13. Micro USB2 B socket (receptacle), J9
  14. 1x14 pin header (2.54mm pitch), J2
  15. 1x6 pin header (2.54mm pitch), J4
  16. 2x6 Pmod connector, J6
  17. 3-pin header (2.54mm pitch), J3
  18. 1x14 pin header (2.54mm pitch), J1

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Storage device name

Content

Notes

Quad SPI Flash, U5

DEMO Design

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I2C Configuration EEPROM, U9

Programmed

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on pin J1-11 pin of bank 1A is (AIN), other are also GPIO's as alternative function
BankConnector DesignatorI/O Signal CountBank VoltageNotes
2J14 I/O's3.3V-
J68 I/O'sPmod connector
5J12 I/O's3.3V-
J29 I/O's2 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors)
1AJ17 7x analog inputs or GPIO's3.3V, 1x Analog reference voltage (AREF)3.3Vanalog pins usable as GPIO's as alternative function

J31 1x analog inputs or GPIO, 1 dedicated analog input1x dedicated analog input
1BJ4JTAG interface and 'JTAGEN' signal (4 5 I/O's)3.3VJTAG enable signal (JTAGEN) on pin J4-2, leave floating when using JTAG interfaceswitch between user I/O pins and JTAG pin functions

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

low active reset input
BankI/O's CountConnected toNotes
24LIS3DH digital motion sensor, U4SPI interface, 2 interrupt lines
81x6 pin header, J4JTAG interface
42 MByte serial configuration memory, U5FPGA configuration memory with active serial (AS) x1 interface
1J2-10, push button S1 1x14 pin header, J1user GPIO's
8Pmod connector, J6user GPIO's
1clock oscillator, U712.0000 MHz reference clock input
1optional clock oscillator, U6oscillator not fitted, footprints available for Microchip MEMS oscillator
591x14 pin header, J2GPIOs (2 I/O's (D11, D12) of bank 2 5 can be pulled-up to 3.3V (4K7 resistors) with 2 1 I/O 's (D12_R) of same Bank or pins can be shared)
1A8LEDs D2 ... D98 x red user LEDs
8FTDI FT2232H JTAG/UART Adapter, U3configurable as GPIO/UART or other serial interfaces
1push button S2user button
1B10pin headers J1, J3GPIOs
56pin headers J1GPIOs
68Pmod connector J6GPIOs
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7198 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
8218 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface

Table 3: General overview of FPGA I/O banks

GPIOs16bit SD-RAM memory interface
BankI/O's CountConnected toNotes
241x14 pin header, J1-
8Pmod connector, J6-
1clock oscillator, U712.0000 MHz reference clock input
1optional clock oscillator, U6footprints available for Microchip MEMS oscillator
591x14 pin header, J22 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6
6188 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
3228 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
6LIS3DH 3-axis accelerometer, U44 I/O's for SPI interface, 2 interrupt lines
1A71x14 pin headers J17 analog inputs or GPIO's, 1 pin analog reference voltage input
2pin headers J168Pmod connector J6and 1 I/O (D11_R) of bank 6
6188 MByte SDRAM 166MHz, U216bit SDRAM memory interface
3228 MByte SDRAM 166MHz, U216bit SDRAM memory interface
6LIS3DH 3-axis accelerometer, U44 I/O's for SPI interface, 2 interrupt lines
1A81x14 pin headers J17 analog inputs or GPIO's, 1 pin analog reference voltage input
2pin headers J11 analog inputs or GPIO, 1 dedicated analog input
1B5pin header J44 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
88LEDs D2 ... D9Red user LEDs
6SPI Flash memory, U54 pins SPI interface, 2 control lines
6FTDI FT2232H JTAG/UART Adapter, U36 pins configurable as GPIO/UART or other serial interfaces
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7198 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
8218 Mbyte SDRAM 166MHz, U2
1User button S2user configurable
1Reset button S1 and pin J2-10low active reset line for FPGA reconfiguration


Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

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JTAG SignalPin on Header J4Note
TCK3-
TDI5-
TDO4-
TMS6-
JTAGEN52-

Table 4: optional JTAG pin header

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Serial Memory U5 PinSignal Schematic NameConnected toNotes
Pin 2, DATA1AS_DATA0FPGA bank 1, pin H2
Data out
Pin 5, DATA0AS_ASDOFPGA bank 1, pin C1Data in
Pin 1, nCSAS_NCSFPGA bank 1, pin D2chip select
Pin 6, DCLKAS_DCLK

FPGA bank 1, pin H1

clock
Pin 6, DCLK






Table 5: Serial configuration memory interface connections

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