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| Bank | I/O's Count | Connected to | Notes |
|---|---|---|---|
| 2 | 4 | 1x14 pin header, J1 | user GPIO's |
| 8 | Pmod connector, J6 | user GPIO's | |
| 1 | clock oscillator, U7 | 12.0000 MHz reference clock input | |
| 1 | optional clock oscillator, U6 | oscillator not fitted, footprints available for Microchip MEMS oscillator | |
| 5 | 9 | 1x14 pin header, J2 | 2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6 |
| 6 | 18 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface |
| 3 | 22 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface |
| 6 | LIS3DH 3-axis accelerometer, U4 | 4 I/O's for SPI interface, 2 interrupt lines | |
| 1A | 8 | 1x14 pin headers J1 | 7 analog inputs or GPIO's, 1 pin analog reference voltage input |
| 2 | pin headers J1 | 1 analog inputs or GPIO, 1 dedicated analog input | |
| 1B | 5 | pin header J4 | 4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND |
| 8 | 8 | LEDs D2 ... D9 | Red user LEDs |
| 6 | SPI QSPI Flash memory, U5 | 6 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization | |
| 6 | FTDI FT2232H JTAG/UART Adapter, U3 | 6 pins configurable as GPIO/UART or other serial interfaces | |
| 1 | Red LED, D10 | Configuration DONE Led (ON when configuration in progress, OFF when configuration is done) | |
| 1 | User button S2 | user configurable | |
| 1 | Reset button S1 and pin J2-10 | low active reset line for FPGA reconfiguration |
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| Serial Memory U5 Pin | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
| Pin 1, CS | F_CS | FPGA bank 8, pin B3 | chip select |
| Pin 6, CLK | F_CLK | FPGA bank 1, pin A3 | clock |
| Pin 5, SI/IO0 | F_DI | FPGA bank 1, pin A2 | data in / out |
| Pin 7, HOLD/IO3 | NSTATUS | FPGA bank 1, pin C4 | data in / out, configuration dual-purpose pin of FPGA |
| Pin 3, WP/IO2 | DEVCLRN | FPGA bank 8, pin B9 | data in / out, configuration dual-purpose pin of FPGA |
| Pin 2, SO/IO1 | F_DO | FPGA bank 8, pin B2 | data in / out |
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The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2 . This in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 7 3 and 8 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
| SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
| Address inputs | A0 ... A13 | bank 83 | - |
| Bank address inputs | BA0 / BA1 | bank 83 | - |
| Data input/output | DQ0 ... DQ15 | bank 76 | - |
| Data mask | DQM0 ... DQM1 | bank 76 | - |
| Clock | CLK | bank 73 | |
| Control Signals | CS | bank 83 | Chip select |
CKE | bank 83 | Clock enable | |
RAS | bank 83 | Row Address Strobe | |
CAS | bank 83 | Column Address Strobe | |
| WE | bank 83 | Write Enable |
Table 6: 16bit SDRAM memory interface
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The FTDI chip U3 converts signals from USB2 .0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 2 6 I/O's of channel A and 6 I/O's of Channel B are routed to FPGA bank 3 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes | |||||
|---|---|---|---|---|---|---|---|---|
| Pin 12, ADBUS0 | TCK | FPGA bank 1, pin H3 | JTAG interface | |||||
| Pin 13, ADBUS1 | TDI | FPGA bank 1, pin H4 | ||||||
| Pin 14, ADBUS2 | TDO | FPGA bank 1, pin J4 | ||||||
| Pin 15, ADBUS3 | TMS | FPGA bank 1, pin J5 | Pin 17, ADBUS4 | ADBUS4 | FPGA bank 3, pin M8 | |||
| user configurable | Pin 20, ADBUS7 | ADBUS7 | FPGA bank 3, pin N8 | user configurable | Pin 32, BDBUS0 | BDBUS0 | FPGA bank 38, pin A4 | user configurable |
| Pin 33, BDBUS1 | BDBUS1 | FPGA bank 38, pin B4 | user configurable | |||||
| Pin 34, BDBUS2 | BDBUS2 | FPGA bank 38, pin B5 | user configurable | |||||
| Pin 35, BDBUS3 | BDBUS3 | FPGA bank 38, pin A6 | user configurable | |||||
| Pin 37, BDBUS4 | BDBUS4 | FPGA bank 38, pin B6 | user configurable | |||||
| Pin 38, BDBUS5 | BDBUS5 | FPGA bank 38, pin A7 | user configurable |
Table 7: FTDI chip interfaces and pins
3-Axis Accelerometer
On the TEI0003 TEI0001 FPGA board there is a 3-axis accelerometer present. This accelerometer is provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.
| Accelerometer U4 Pin | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
| Pin 11, INT1 | SEN_INT1 | FPGA bank 13, pin B1J5 | Interrupt lines |
| Pin 9, INT2 | SEN_INT2 | FPGA bank 13, pin C2L4 | |
| Pin 6, SDA/SDI/SDO | SEN_SDI | FPGA bank 13, pin G2J7 | SPI interface |
| Pin 7, SDO/SA0 | SEN_SDO | FPGA bank 13, pin G1K5 | |
| Pin 4, SCL/SPC | SEN_SPC | FPGA bank 13, pin F3J6 | |
| Pin 8, CS | SEN_CS | FPGA bank 13, pin D1L5 | |
| Pin 13, ADC3 | ADC3 | 5V | Sense 5V input voltage |
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| Clock Source | Schematic Name | Frequency | Clock Input Destination |
|---|---|---|---|
| Microchip MEMS Oscillator, U7 | CLK12M | 12.0000 MHz | FTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin M2H6 |
| optional Microchip MEMS Oscillator, U6 (not fitted) | CLK_X | - | FPGA SoC bank 62, pin E15G5 |
Table 9: Clock sources overview
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| LED | Color | Signal Schematic Name | FPGA | Notes |
|---|---|---|---|---|
| D1 | Green | - | - | Indicating 3.3V board supply voltage |
| D2 | Red | 'LED1' | bank 68, pin M6pin A8 | user |
| D3 | Red | 'LED2' | bank 68, pin T4pin A9 | user |
| D4 | Red | 'LED3' | bank 68, pin T3A11 | user |
| D5 | Red | 'LED4' | bank 68, pin R3A10 | user |
| D6 | Red | 'LED5' | bank 68, pin T2pin B10 | user |
| D7 | Red | 'LED6' | bank 68, pin R4C9 | user |
| D8 | Red | 'LED7' | bank 68, pin N5pin C10 | user |
| D9 | Red | 'LED8' | bank 68, pin N3pin D8 | user |
| D10 | Red | 'CONF_DONE' | bank 68, pin H14C5 | indication configuration is DONE when LED is off |
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| Button | Signal Schematic Name | FPGA | Notes |
|---|---|---|---|
| S1 | 'USER_BTN' | bank 38, pin N6E6 | user configurable |
| S2 | 'RESET' | bank 18, pin H5E7 | system FPGA reset |
Table 11: Push buttons of the module
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The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.
The TEI0003 TEI0001 module needs one single power supply of 5.0V nominal.
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Power Consumption
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