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Table of Contents
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The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card (PCIe 2.0 or higher) integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA chipSoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. The board offers a SO-DIMM socket on the board for standard DDR3 SDRAM extension memory module.
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Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation. |
Key Features
- Xilinx ZynqKintex-7000 XC7Z0357 XC7K160T, XC7Z045 XC7K325T or XC7Z100 SoCRugged for shock and high vibrationXC7K410T FPGA SoC
- Large number of configurable I/Os are provided via rugged high-speed stacking stripsHPC FMC connector
- Dual ARM Cortex-A9 MPCore
- 1 GByte RAM (32-Bit wide DDR3)
- 32 MByte QSPI Flash memory
- 2 x Hi-Speed USB2 ULPI transceiver PHY
- 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
- 4 GByte eMMC (optional up to 64 GByte)
- 2 x MAC-address EEPROMs
- Optional 2x 64 MByte HyperFLASH or 2x 8 MByte HyperRAM (max 2x 32 MByte HyperRAM)
- Temperature compensated RTC (real-time clock)
- Si5338A programmable quad PLL clock generator for GTX transceiver clocks
- Plug-on module with 3 x 160-pin high-speed strips
- 16 GTX high-performance transceiver
- 2x GT transceiver clock inputs
- 254 FPGA I/O's (125 LVDS pairs)
- On-board high-efficiency switch-mode DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Evenly-spread supply pins for good signal integrity
- User LED
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Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
24LC128-I/ST | not programmed | User content |
24AA025E48 EEPROM's | User content not programmed | Valid MAC Address from manufacturer |
Si5338A OTP Area | not programmed | - |
eMMC Flash Memory | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | demo design | - |
HyperFlash Memory | not programmed | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
Table 1: Initial delivery state of programmable devices on the module
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Zynq-7000 SoC's I/O banks signals connected to the B2B connectors:
Bank | Type | B2B Connector | I/O Signal Count | Differential | Voltage | Notes |
---|---|---|---|---|---|---|
10 | HR | J3 | 44 | 22 | User | Max voltage 3.3V |
11 | HR | J3 | 40 | 20 | User | Max voltage 3.3V |
12 | HR | J2 | 40 | 20 | User | Max voltage 3.3V |
13 | HR | J2 | 40 | 20 | User | Max voltage 3.3V |
33 | HP | J1 | 48 | 23 | User | Max voltage 1.8V |
34 | HP | J1 | 42 | 20 | User | Max voltage 1.8V |
Table 2: General overview of board to board I/O signals
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The Xilinx Zynq-7000 SoC used on the TE0782 module has 16 MGT transceiver lanes. All of them are wired directly to B2B connectors J1 and J3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane with data transmission rates up to 12.5Gb/s per lane (Xilinx GTX transceiver). Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Bank | Type | Lane | Signal Name | B2B Pin | FPGA Pin |
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109 | GTX | 0 |
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110 | GTX | 0 |
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111 | GTX | 0 |
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112 | GTX | 0 |
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Table 3: MGT lanes
There are 2 clock sources for the GTX transceivers. MGT_CLK1 and MGT_CLK4 are connected directly to B2B connector J3 and J1, so the clock can be provided by the carrier board. Clocks MGT_CLK0, MGT_CLK3, MGT_CLK5 and MGT_CLK6 are provided by the on-board clock generator (U2). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.
Bank | Type | Clock signal | Source | FPGA Pin | Notes |
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109 | GTX | MGT_CLK3_P | U2, CLK3A | MGTREFCLK1P_109, AF10 | Supplied by on-board Si5338A |
MGT_CLK3_N | U2, CLK3B | MGTREFCLK1N_109, AF9 | |||
110 | GTX | MGT_CLK0_P | U2, CLK2A | MGTREFCLK0P_110, AA8 | Supplied by on-board Si5338A |
MGT_CLK0_N | U2, CLK2B | MGTREFCLK0N_110, AA7 | |||
MGT_CLK1_N | J3-39 | MGTREFCLK1P_110, AC8 | Supplied by B2B connector J3 | ||
MGT_CLK1_P | J3-37 | MGTREFCLK1N_110, AA7 | |||
111 | GTX | MGT_CLK4_N | J1-40 | MGTREFCLK0P_111, U8 | Supplied by B2B connector J1 |
MGT_CLK4_P | J1-38 | MGTREFCLK0N_111, U7 | |||
MGT_CLK5_P | U2, CLK1A | MGTREFCLK1P_111, W8 | Supplied by on-board Si5338A | ||
MGT_CLK5_N | U2, CLK1B | MGTREFCLK1N_111, W7 | |||
112 | GTX | MGT_CLK6_P | U2, CLK0A | MGTREFCLK0P_112, N8 | Supplied by on-board Si5338A |
MGT_CLK6_N | U2, CLK0B | MGTREFCLK0N_112, N7 |
Table 4: MGT reference clock sources
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JTAG access to the Xilinx Zynq-7000 is provided through B2B connector J3.
JTAG Signal | B2B Connector Pin |
---|---|
TMS | J3-142 |
TDI | J3-147 |
TDO | J3-148 |
TCK | J3-141 |
Table 5: Zynq JTAG interface signals
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JTAG access to the LCMXO2-1200HC System Controller CPLD U14 is provided through B2B connector J3.
JTAG Signal | B2B Connector Pin |
---|---|
M_TMS | J3-82 |
M_TDI | J3-87 |
M_TDO | J3-88 |
M_TCK | J3-81 |
Table 6: System Controller CPLD JTAG interface signals
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Special purpose pins are connected to System Controller CPLD and have following default configuration:
Pin Name | Direction | Function | Default Configuration |
---|---|---|---|
BOOTMODE | in | in | signal forwarded to MIO9 and currently used as UART RX line |
CONFIGX | in | out | signal forwarded to MIO8 and currently used as UART TX line |
RESIN | in | nRESET | external Board Reset |
M_TDO | out | CPLD JTAG interface | - |
M_TDI | in | ||
M_TCK | in | ||
M_TMS | in | ||
JTAGENB | in | enable JTAG | pull high for programming SC CPLD firmware |
I2C_SCL | in / out | I²C data line | I²C bus of board |
I2C_SDA | in | I²C clock | |
CPLD_IO | in / out | user GPIO | currently not used |
ETH1_RESET | out | reset GbE PHY U18 | see current SC CPLD firmware |
OTG-RST | out | reset USB2 PHYs U4 and U8 | see current SC CPLD firmware |
RTC_INT | in | interrupt | interrupt from RTC |
PS_SRST | out | Zynq control signal | reset PS of Zynq-7000 SoC |
DONE | in | PL configuration completed | |
PROG_B | out | PL configuration reset signal | |
INIT | in | Low active FPGA initialization pin or configuration error signal | |
PS_POR | out | PS power-on reset | |
BM0/MIO5 | out | Bootmode Pins currently configured in SC CPLD firmare to boot from QSPI Flash | |
BM2/MIO4 | out | ||
BM3/MIO2 | out | ||
MIO8 | in | user MIO pins | currently used as UART interface |
MIO9 | out | ||
MMC_RST | out | Reset MMC Flash | see current SC CPLD firmware |
ETH1-RESET33 | in | reset GbE PHY U18 | reset signal from Zynq-7000 level shifted to 1.8V |
OTG-RST33 | in | reset USB2 PHYs | reset signal from Zynq-7000 level shifted to 1.8V |
LED1 ... LED2 | out | LED status signal | see current CPLD firmware |
CPLD_GPIO0 ... CPLD_GPIO5 | in / out | user GPIO | currently not used |
EN_1V | out | Power control | enable signal DCDC U13 '1V' |
PG_1V | in | power good signal DCDC U13 '1V' | |
EN_1.0V_MGT | out | enable signal DCDC U16 '1.0V_MGT' | |
PG_1.0V_MGT | in | power good signal DCDC U16 '1.0V_MGT' | |
EN_1.2V_MGT | out | enable signal DCDC U16 '1.2V_MGT' | |
PG_1.2V_MGT | in | power good DCDC U16 '1.2V_MGT' | |
EN_1.8V | out | enable signal DCDC U16 '1.8V' | |
PG_1.8V | in | power good signal DCDC U16 '1.8V' | |
EN_3.3V | out | enable signal DCDC U16 '3.3V' | |
PG_3.3V | in | power good signal DCDC U16 '3.3V' | |
PG_1V5 | in | power good signal DCDC U23 '1.5V' |
Table 7: System Controller CPLD special purpose pins.
See also TE0782 CPLD reference Wiki page.
Default PS MIO Mapping
MIO | Function | Connected to |
---|---|---|
0 | USB2 PHYs Reset | SC CPLD (used as level translator) |
1 | QSPI0 | SPI Flash-CS |
2 | QSPI0 | SPI Flash-DQ0 |
3 | QSPI0 | SPI Flash-DQ1 |
4 | QSPI0 | SPI Flash-DQ2 |
5 | QSPI0 | SPI Flash-DQ3 |
6 | QSPI0 | SPI Flash-SCK |
7 | Ethernet PHY1 Reset | SC CPLD (used level translator) |
8 | UART TX | output, muxed to B2B by the SC CPLD |
9 | UART RX | input, muxed to B2B by the SC CPLD |
10 | SDIO1 D0 | eMMC DAT0 |
11 | SDIO1 CMD | eMMC CMD |
12 | SDIO1 CLK | eMMC CLK |
13 | SDIO1 D1 | eMMC DAT1 |
14 | SDIO1 D2 | eMMC DAT2 |
15 | SDIO1 D3 | eMMC DAT3 |
16..27 | ETH0 | Ethernet RGMII PHY |
28..39 | USB0 | USB0 ULPI PHY |
40...51 | USB1 | USB1 ULPI PHY |
52 | ETH0 MDC | - |
53 | ETH0 MDIO | - |
Table 8: Zynq PS MIO mapping
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The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11), the 125MHz output clock of both PHYs are connected to Zynq's PL bank 35.
ETH1 PHY connection:
PHY PIN | Zynq PS / PL | System Controller CPLD | Notes |
---|---|---|---|
MDC/MDIO | MIO52, MIO53 | - | - |
LED0 | Bank 35, Pin B12 | - | - |
LED1 | Bank 35, Pin C12 | - | - |
Interrupt | Bank 35, Pin A15 | - | - |
CONFIG | Bank 35, Pin F14 | - | When pin connected to GND, PHY Address is strapped to 0x00 by default |
RESETn | - | Pin 53 | ETH1_RESET33 (MIO7) -> SC CPLD -> ETH1_RESET |
RGMII | MIO16..MIO27 | - | |
MDI | - | - | on B2B J2 connector |
Table 9: General overview of the Gigabit Ethernet1 PHY signals
ETH2 PHY connection:
PHY PIN | Zynq PS / PL | System Controller CPLD | Notes |
---|---|---|---|
MDC/MDIO | Bank 35, Pin C17/B17 | - | - |
LED0 | Bank 35, Pin K15 | - | - |
LED1 | Bank 35, Pin B16 | - | - |
Interrupt | Bank 35, Pin A17 | - | - |
CONFIG | Bank 35, Pin E15 | - | When pin connected to GND, PHY Address is strapped to 0x00 by default |
RESETn | Bank 35, Pin B15 | - | - |
RGMII | Bank 9 | - | - |
MDI | - | - | on B2B J2 connector |
Table 10: General overview of the Gigabit Ethernet2 PHY signals
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The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).
USB0 PHY connection:
PHY Pin | Zynq PS / PL | CPLD | B2B Connector J2 | Notes |
---|---|---|---|---|
ULPI | MIO28..39 | - | - | Zynq USB0 MIO pins are connected to the PHY |
REFCLK | - | - | - | 52MHz from on board oscillator (U7) |
REFSEL[0..2] | - | - | - | 000 GND, select 52MHz reference Clock |
RESETB | MIO0 | OTG_RESET33 | - | OTG_RESET33 -> SC CPLD -> OTG_RESET |
CLKOUT | MIO36 | - | - | Connected to 1.8V selects reference clock operation mode |
DP,DM | - | - | USB1_D_P, USB1_D_N | USB Data lines |
CPEN | - | - | VBUS1_V_EN | External USB power switch active high enable signal |
VBUS | - | - | USB1_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic. |
ID | - | - | OTG1_ID | For an A-Device connect to ground, for a B-Device left floating |
Table 11: General overview of the USB0 PHY signals
USB1 PHY connection:
PHY Pin | Zynq PS / PL | CPLD | B2B Connector J2 | Notes |
---|---|---|---|---|
ULPI | MIO40..51 | - | - | Zynq USB1 MIO pins are connected to the PHY |
REFCLK | - | - | - | 52MHz from on board oscillator (U7) |
REFSEL[0..2] | - | - | - | 000 GND, select 52MHz reference Clock |
RESETB | MIO0 | OTG_RESET33 | - | OTG_RESET33 -> SC CPLD -> OTG_RESET |
CLKOUT | MIO48 | - | - | Connected to 1.8V selects reference clock operation mode |
DP,DM | - | - | USB2_D_P, USB2_D_N | USB Data lines |
CPEN | - | - | VBUS2_V_EN | External USB power switch active high enable signal |
VBUS | - | - | USB2_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic. |
ID | - | - | OTG2_ID | For an A-Device connect to ground, for a B-Device left floating |
Table 12: General overview of the USB1 PHY signals
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I2C addresses for on-board components:
Device | IC | Designator | I2C-Address | Notes |
---|---|---|---|---|
EEPROM | 24LC128-I/ST | U26 | 0x53 | user data |
EEPROM | 24AA025E48T-I/OT | U22 | 0x50 | MAC address EEPROM |
EEPROM | 24AA025E48T-I/OT | U24 | 0x51 | MAC address EEPROM |
RTC | ISL12020MIRZ | U17 | 0x6F | Temperature compensated real time clock |
Battery backed RAM | ISL12020MIRZ | U17 | 0x57 | Integrated in RTC |
PLL | SI5338A-B-GMR | U2 | 0x70 | - |
SC CPLD | LCMXO2-1200HC-4TG100I | U14 | user | - |
Table 13: Address table of the I2C bus slave devices
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Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.
Signal | Frequency | Notes |
---|---|---|
IN1/IN2 | user | External clock signal supply from B2B connector J3, pins J3-38 / J3-40 |
IN3 | 25.000000 MHz | Fixed input clock signal from reference clock generator SiT8008BI-73-18S-25.000000E (U3) |
IN4 | - | LSB of the default I2C address, wired to ground mean address is 0x70 |
IN5 | - | Not connected |
IN6 | - | Wired to ground |
CLK0 A/B | - | reference clock 0 of Bank 112 GTX |
CLK1 A/B | - | reference clock 1 of Bank 111 GTX |
CLK2 A/B | - | reference clock 0 of Bank 110 GTX |
CLK3 A/B | - | reference clock 1 of Bank 109 GTX |
Table 14: General overview of the on-board quad clock generator I/O signals
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The module has following reference clock signals provided by on-board oscillators and external source from carrier board:
Clock Source | Schematic Name | Frequency | Clock Destination |
---|---|---|---|
SiTime SiT8008AI oscillator, U61 | PS_CLK | 33.333333 MHz | Zynq SoC U1, pin A22 |
SiTime SiT8008BI oscillator, U21 | - | 25.000000 MHz | Quad PLL clock generator U2, pin 3 |
SiTime SiT8008AI oscillator, U7 | - | 52.000000 MHz | USB2 PHYs U4 and U8, pin 26 |
SiTime SiT8008BI oscillator, U11 | - | 25.000000 MHz | GbE PHYs U18 and U20, pin 34 |
Table 15: Reference clock signals
On-board LEDs
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Red | System Controller CPLD U14, bank 3 | Exact function is defined by SC CPLD firmware |
D2 | Green | System Controller CPLD U14, bank 3 |
Table 16: On-board LEDs
Power and Power-on Sequence
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Power supply with minimum current capability of 4A for system startup is recommended.
Power Consumption
Power Input | Typical Current |
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VIN | TBD* |
C3.3V | TBD* |
Table 17: Power consumption
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Power Rails
Power Rail Name on B2B Connector | J1 Pins | J2 Pins | J3 Pins | Direction | Notes |
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VIN | - | 165, 166, 167, 168 | - | Input | external power supply voltage |
C3.3V | - | 147, 148 | - | Input | external 3.3V power supply voltage |
3.3V | - | 111, 112, 123, 124, 135 136 169, 170, 171, 172 | - | Output | internal 3.3V voltage level |
1.8V | 169, 170, 171, 172 | - | - | Output | internal 1.8V voltage level |
VCCIO_10 | - | - | 99, 100 | Input | high range I/O bank voltage |
VCCIO_11 | - | - | 159, 160 | Input | high range I/O bank voltage |
VCCIO_12 | - | 159, 160 | - | Input | high range I/O bank voltage |
VCCIO_13 | - | 99, 100 | - | Input | high range I/O bank voltage |
VCCIO_33 | 99, 100 | - | - | Input | high performance I/O bank voltage |
VCCIO_34 | 159, 160 | - | - | Input | high performance I/O bank voltage |
VBAT_IN | - | - | 124 | Input | backup battery voltage |
Table 18: Module power rails
Bank Voltages
Bank | Schematic Name | Voltage | Range | Notes |
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0 | - | 3.3 V | - | FPGA configuration |
502 | - | 1.5 V | - | DDR3-RAM port |
109 / 110 / 111 / 112 | - | 1.2 V | - | MGT |
500 / 501 | - | 3.3 V | - | MIO banks |
9 (HR) | - | 1.8 V | 1.2V to 3.3V | ETH2 RGMII |
10 (HR) | VCCIO_10 | user | 1.2V to 3.3V | - |
11 (HR) | VCCIO_11 | user | 1.2V to 3.3V | - |
12 (HR) | VCCIO_12 | user | 1.2V to 3.3V | - |
13 (HR) | VCCIO_13 | user | 1.2V to 3.3V | - |
33 (HP) | VCCIO_33 | user | 1.2V to 1.8V | - |
34 (HP) | VCCIO_34 | user | 1.2V to 1.8V | - |
35 (HP) | - | 1.8 V | 1.2V to 1.8V | Hyper-RAM, Ethernet, I²C |
Table 19: Module I/O bank voltages
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Variants Currently In Production
Trenz shop TE0782 overview page | |
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English page | German page |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
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VIN supply voltage | -0.3 | 15 | V | LTM4644 datasheet |
C3.3V supply voltage | -0.3 | 3.6 | V | LTM4644 datasheet |
VBAT supply voltage | -0.3 | 6 | V | TPS780180 datasheet |
PS I/O supply voltage, VCCO_PSIO | -0.5 | 3.6 | V | Xilinx document DS191 |
PS I/O input voltage | -0.4 | VCCO_PSIO + 0.55 | V | Xilinx document DS191 |
HP I/O bank supply voltage, VCCO | -0.5 | 2.0 | V | Xilinx document DS191 |
HP I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS191 |
HR I/O bank supply voltage, VCCO | -0.5 | 3.6 | V | Xilinx document DS191 |
HR I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS191 |
Reference Voltage pin | -0.5 | 2 | V | Xilinx document DS191 |
Differential input voltage | -0.4 | 2.625 | V | Xilinx document DS191 |
MGT reference clocks absolute input voltage | -0.5 | 1.32 | V | Xilinx document DS191 |
MGT absolute input voltage | -0.5 | 1.26 | V | Xilinx document DS191 |
Voltage on SC CPLD pins | -0.5 | 3.75 | V | Lattice Semiconductor MachXO2 datasheet |
Storage temperature | -40 | +85 | °C | See eMMC MTFC4GMVEA datasheet |
Table 20: Module absolute maximum ratings
Recommended Operating Conditions
Parameter | Min | Max | Units | Notes |
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VIN supply voltage | 11.4 | 12.6 | V | LTM4644 datasheet, 12V nominal |
C3.3V supply voltage | 3.3 | 3.465 | V | LCMXO2-256HC, LTM4644 datasheet |
VBAT supply voltage | 2.2 | 5.5 | V | TPS780180 datasheet |
PS I/O supply voltage, VCCO_PSIO | 1.710 | 3.465 | V | Xilinx document DS191 |
PS I/O input voltage | –0.20 | VCCO_PSIO + 0.20 | V | Xilinx document DS191 |
HP I/O banks supply voltage, VCCO | 1.14 | 1.89 | V | Xilinx document DS191 |
HP I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx document DS191 |
HR I/O banks supply voltage, VCCO | 1.14 | 3.465 | V | Xilinx document DS191 |
HR I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx document DS191 |
Differential input voltage | -0.2 | 2.625 | V | Xilinx document DS191 |
Voltage on SC CPLD pins | -0.3 | 3.6 | V | Lattice Semiconductor MachXO2 datasheet |
Operating Temperature Range | -40 | 85 | °C | Xilinx document DS191, industrial grade Zynq temperarure range |
Table 21: Recommended operating conditions
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Hardware Revision History
Date | Revision | Notes | PCN Link | Documentation Link |
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- | 02 | current available board revision | - | TE0782-02 |
2015-05-27 | 01 | Prototype only | - | - |
Table 22: Hardware revision history table
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