Page History

...

<!--
General Design description
 -->

Zynq PS Design with DDR Less FSBL Example.

Key Features

<!--
Add Basic Key Features of the design (should be tested)
 -->

...

<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
  -->

Release Notes and Know Issues

...

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image RemovedImage Added
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Basic Information, see TE0722 Getting Started

Programming

<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

...

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-bootfsbl_app
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

...

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from SD QSPI into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

...

1. bitfile from qsi, 3. FSBL starts application

Baremetal App

Note: UART over J2 is used, this is only available, if PL part is configured.

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Output:
   1. TODO
      
   2. Default output appears only one time. Reboot device: force ResN Pin to GND for short time, location see: TE0722 Getting Started
      Image Added
   3. alternately Hello TE0722 loop (for 100sec): uncomment loop in fsbl example (fsbl_hooks.c) and regenerate FSBL and Boot.bin
      Image Added
      

System Design - System Design - Vivado

<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

Block Design

Image Added

PS Interfaces

Constrains

Basic module constrains

...

Constrains

Basic module constrains

#
# Common BITGEN related settings for TE0722
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

set_property PACKAGE_PIN K15 [get_ports UART_0_txd]
set_property PACKAGE_PIN L13  [get_ports UART_0_rxd]

set_property IOSTANDARD LVCMOS33 [get_ports UART_0_*]

Design specific constrain

Software Design - SDK/HSI

...

...