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DateVivadoProject BuiltAuthorsDescription
2018-09-052018.2te0712-test_board-vivado_2018.2-build_03_20180906071356.zip
te0712-test_board_noprebuilt-vivado_2018.2-build_03_20180906071434.zip
John Hartfiel
  • chance nlock block design: qspi clks, clock wizard(REV01 only)
  • change uiming Constrainstiming constrains
  • Add add hello_tE0712 te0712 application
  • New new SREC bootloader version
  • Linux change linux device tree
2018-05-252017.4te0712-test_board-vivado_2017.4-build_10_20180525155402.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_10_20180525155555.zip
John Hartfiel
  • solved eth issue for REV01
  • changed design + second design for REV01
2018-04-122017.4te0712-test_board-vivado_2017.4-build_07_20180412081225.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip
John Hartfiel
  • Bugfix Constrain File bugfix constrain file - ETH REFCLK, Timingtiming
2018-03-282017.4te0712-test_board-vivado_2017.4-build_07_20180328145151.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zip
John Hartfiel
  • new assembly variant
2018-01-082017.4te0712-test_board-vivado_2017.4-build_02_20180108155712.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zip
John Hartfiel
  • No Design no design changes
  • small constrain changes
2017-12-152017.2te0712-test_board-vivado_2017.2-build_07_20171215172447.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zip
John Hartfiel
  • Add add SI5338 initialisation with MCS
  • Add add Ethernet IP
2017-11-072017.2te0712-test_board-vivado_2017.2-build_05_20171107172917.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zip
John Hartfiel
  • Add Wiki Link add wiki link in Boart Part Files
  • Set Correct Short Link set correct short link for te0712-02-200-2c
2017-10-052017.2te0712-test_board-vivado_2017.2-build_03_20171005082148.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zip
John Hartfiel
  • initial release

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HTML
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
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Block Design

REV02

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REV01

Same as REV02 but 50 MHz ETH REV CLK is generated from MIG output with 180° Phase shift.

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Constrains

Basic module constrains

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U-Boot

Code Block
languagejs

#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

/* ethernet - axi_ethernetlite_0 */
#undef CONFIG_PHY_XILINX
#undef XILINX_EMACLITE_BASEADDR    0x40E00000
#undef CONFIG_MII
#undef CONFIG_NET_MULTI
#undef CONFIG_NETCONSOLE    1
#undef CONFIG_SERVERIP    192.168.150.127
#undef CONFIG_IPADDR

/* PREBOOT */
#define CONFIG_PREBOOT    "echo U-BOOT for petalinux;setenv preboot; echo;"

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DateDocument RevisionAuthorsDescription

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  • 2018.2 release (working in process)

v.28John Hartfiel
  • Design update

v.27John Hartfiel
  • Know Issues
  • Documentation

v.23John Hartfiel
  • Design Update

v.22John Hartfiel
  • Know Issue for PCB REV01 only
  • Fix typo
  • New assembly variant
2018-02-13v.19John Hartfiel
  • Release 2017.4
2018-01-08v.16John Hartfiel
  • Add SCU source path
2017-12-15v.15John Hartfiel
  • Update Design and Description
2017-11-07v.11John Hartfiel
  • Update Design Files
2017-10-06v.10John Hartfiel
  • small Document Update
2017-10-05

v.8

John Hartfiel
  • Release 2017.2
2017-09-11v.1

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created-user

  • Initial release

All

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