Page History
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On-board Si5338 clock generator chip is used to generate clocks with 25 MHz oscillator connected to the pin IN3 as input reference. There is a I2C bus connection between the FPGA bank 14 (master) and clock generator chip (slave) which can be used to program output frequencies. See the reference design for more information.
| CLK Output | FPGA Bank | FPGA Pin | IO Standard | Net Name | Default Freq | Note |
|---|---|---|---|---|---|---|
| CLK0 | - | - | - | - | -- | N.C. |
| CLK1 | - | - | - | - | -- | N.C. |
| CLK2 | 216 | F6/E6 | Auto | MGT_CLK0_P/N | 125 MHz | GTP transceiver clock. |
| CLK3 | 35 | H4/G4 | LVDS | PLL_CLK_P/N | 200 MHz | AC coupled, board termination |
On-board Peripherals
32 MByte Quad SPI Flash Memory
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TE0713-01 is equipped with the FTDI FT600Q high performance USB 3.0-to-FIFO interface bridge chip.
| Info |
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SSTX_P and SSTX_N ar swapped on the PCB,this will be corrected automatically on link training on USB3 |
Power and Power-On Sequence
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||
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| v.9 | John Hartfiel |
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| v.8 | John Hartfiel |
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| 2017-05-28 | v.6 | Jan Kumann |
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| 2017-02-07 | v.1 | Jan Kumann |
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