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*.img

Debian Image for SD-Card

File

File-Extension

Description

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TEF1001 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Generate Programming Files with HSI/SDK
   
   1. Start with TE Scripts on Vivado TCL: TE::sw_run_hsi
      (optional) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk to generate files manually
      Note: See SDK Projects
   2. (optional )Copy "prebuilt\software\<short dir>\srec_spi_bootloader.elf" into "\firmware\microblaze_0" (replace shipped one) and regenerate design again (HW (Step5)+SW(Step6 only a.))

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

1. Connect JTAG and Power ON PC
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_tef1001
4. Reboot PC

SD

Not supported.

JTAG

• Connect Vivado HW Manager and program FPGA
  Note: PCIe enumeration will be not done in this case. SREC Bootloader need Hello TEF1001 application on QSPI Flash for output

Usage

1. Prepare HW like described on section Programming
2. Power On PCB
   Note: 1. FPGA Load Bitfile  into FPGA, modified SREC Bootloader configure SI5338 and load application from QSPI into DDR (Depends on linker script)

JTAG/UART Console:

• Launch the XSDB console on SDK (Xilinx → XSCT Console):
  • type: connect
  • type: targets -set -filter {name =~ "MicroBlaze Debug*"} -index 0
  • type: jtagterminal -start
  • Separat console starts:
    Image Removed

...

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TEC0330 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Generate Programming Files with HSI/SDK
   
   1. Start with TE Scripts on Vivado TCL: TE::sw_run_hsi
      (optional) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk to generate files manually
      Note: See SDK Projects
   2. (optional ) Copy "prebuilt\software\<short dir>\srec_spi_bootloader.elf" into "\firmware\microblaze_0" (replace shipped one) and regenerate design again (HW (Step5)+SW(Step6 only a.))
   3. (optional ) for SI5338 reprogramming with  MCS:
      1.   Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk to generate files manually
      2. New Application with Project Name "SCU" and Processor "microblaze_mcs_0_microblaze_I", select TE Application "SCU-Firmware"
      3. Create elf file
      4. Copy "workspace\sdk\SCU\<release or debug>\SCU.elf" into "\firmware\microblaze_mcs_0" (replace shipped one) and regenerate design again (HW (Step5)+SW(Step6 only a.))

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

1. Connect JTAG and Power ON PC
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_mcsfile -swapp hello_tec0330
4. Reboot PC

SD

Not supported.

JTAG

• Connect Vivado HW Manager and program FPGA
  Note: PCIe enumeration will be not done in this case. SREC Bootloader need Hello TEF1001 application on QSPI Flash for output

Usage

1. Prepare HW like described on section Programming
2. Power On PCB
   Note: 1. FPGA Load Bitfile  into FPGA,MCS configure SI5338 and starts microblaze design, modified SREC Bootloader load application from QSPI into DDR (Depends on linker script)

JTAG/UART Console:

• Launch the XSDB console on SDK (Xilinx → XSCT Console):
  • type: connect
  • type: targets -set -filter {name =~ "MicroBlaze Debug*"} -index 0
  • type: jtagterminal -start
  • Separat console starts:
    Image Added

Vivado HW Manager:

1. Open Vivado HW Manager
2. Add VIO to Dashboard:
3. Set Radix to unsigned integer for FMeterCLKs (fm_*). Note measurement is not accurate
   
4. Control:
   
   1. MCS Reset
   2. MIG Reset
      
5. Read: All SI5338 CLKs (Unit Hz), PCIe Core User Link Up signal, MIG MMCM Lock signal, MIG Init Calibration Done signal
   Image Added
   

 PC:

• Use for example PCI-Z (Win) or KInfoCenter (Linux) to detect PCIe Card

Image Added

System Design - Vivado

1. Open Vivado HW Manager
2. Add VIO to Dashboard:
3. Set Radix to unsigned integer for FMeterCLKs (labt_SI_*)
   
4. Control:
   
   1. USER LEDs are selectable
      Note USR_CPLD_LED on PCB REV1 and REV02, USR_LED Matrix only on REV02
      
   2. Optional PCIe Core Reset (on FPGA only)
   3. Optional System Reset (on FPGA only)
5. Read: All SI5338 CLKs (Unit Hz), PCIe Cor MMCM Lock signal, MIG MMCM Lock signal, MIG Init Calibration Done
   Image Removed
   

 PC:

• Use for example PCI-Z (Win) or KInfoCenter (Linux) to detect PCIe Card

Image Removed

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title Block Design
Image Removed

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

Block Design

Scroll Title
anchor Figure_BD title Block Design
Image Added

Constrains

Basic module constrains

#
# Default common settings that do not depend assembly variant
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]

set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]

Design specific constrain

#----------
#IIC to CPLD
set_property PACKAGE_PIN W29 [get_ports SCF_0_cpld_25_scl]
set_property PACKAGE_PIN W26 [get_ports SCF_0_cpld_19_oe]
set_property PACKAGE_PIN V29 [get_ports SCF_0_cpld_24_sda]

#----------
#USER LED Matrix
#

#USER LEDS CONNECTED TO A FMC_ADJ VCCO BANK (default config 1.8V)
set_property PACKAGE_PIN K25 [get_ports {USR_LED[0]}]
set_property PACKAGE_PIN K26 [get_ports {USR_LED[1]}]
set_property PACKAGE_PIN P26 [get_ports {USR_LED[2]}]
set_property PACKAGE_PIN R26 [get_ports {USR_LED[3]}]
set_property PACKAGE_PIN N16 [get_ports {USR_LED[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[4]}]

#USER LEDS CONNECTED TO A 1.8V VCCO BANK
set_property PACKAGE_PIN J26 [get_ports {USR_LED[5]}]
set_property PACKAGE_PIN H26 [get_ports {USR_LED[6]}]
set_property PACKAGE_PIN E26 [get_ports {USR_LED[7]}]
set_property PACKAGE_PIN A24 [get_ports {USR_LED[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[8]}]

#USER LED CONNECTED TO A FMC_ADJ VCCO BANK (default config 1.8V)
set_property PACKAGE_PIN F19 [get_ports {USR_LED[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[9]}]


#----------
#USER LED over CPLD
# FEX11SCF_0_cpld_25_scl]
set_property PACKAGE_PINIOSTANDARD B21LVCMOS18 [get_ports {USR_CPLD_LED[0]}]SCF_0_cpld_19_oe]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_CPLD_LED[0]}SCF_0_cpld_24_sda]
#----------
#CLK DDR3
#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
##set#PCIe
set_property PACKAGE_PIN AB11E33 [get_ports CLKFEX_DDR3_200MHz_clk_p4_N]
##setset_property PACKAGE_PINIOSTANDARD AC11LVCMOS18 [get_ports CLKFEX_DDR3_200MHz_clk_n4_N]
##setset_property IOSTANDARD DIFF_SSTL15PACKAGE_PIN AD6 [get_ports {CLK_DDR3PCIe_200MHz100MHz_clk_p[0]
##set}]
#todo check auto placement:
set_property IOSTANDARD DIFF_SSTL15CLOCK_DEDICATED_ROUTE FALSE [get_ports CLK_DDR3_200MHz_clk_nnets msys_i/axi_pcie3_0/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/pipe_txoutclk_out]
#----------
#QSPI#Revision ID
set_property PACKAGE_PIN C23AP27 [get_ports {spi_rtl_ss_ioREV_ID[0]}]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18AN27 [get_ports {spi_rtl_ss_io[0REV_ID[1]}]
set_property PACKAGE_PIN B24AP26 [get_ports spi_rtl_io0_io]
set_property PACKAGE_PIN A25 [get_ports spi_rtl_io1_io{REV_ID[2]}]
set_property PACKAGE_PIN B22AP25 [get_ports spi_rtl_io2_io_ports {REV_ID[3]}]
set_property PACKAGE_PINIOSTANDARD A22LVCMOS18 [get_ports spi_rtl_io3_io]{REV_ID[*]}]
#----------
#QSPI
set_property IOSTANDARDPACKAGE_PIN LVCMOS18AL33 [get_ports {spi_rtl_io0ss_io[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {spi_rtl_io1ss_io[0]}]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18AN33 [get_ports spi_rtl_io2io0_io]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18AN34 [get_ports spi_rtl_io3io1_io]
#----------
#IIC to CPLD
set_property PACKAGE_PIN G26AK34 [get_ports SCFspi_cpldrtl_1io2_sclio]
set_property PACKAGE_PIN F25AL34 [get_ports SCFspi_cpldrtl_14io3_oeio]
set_property PACKAGE_PINIOSTANDARD G25LVCMOS18 [get_ports SCFspi_cpldrtl_16io0_sdaio]
set_property IOSTANDARD LVCMOS18 [get_ports SCFspi_cpldrtl_1io1_sclio]
set_property IOSTANDARD LVCMOS18 [get_ports SCFspi_cpldrtl_14io2_oeio]
set_property IOSTANDARD LVCMOS18 [get_ports SCFspi_cpldrtl_16io3_sdaio]
#----------
#SI5338 CLKs#CLKS
##SI5338_0_DDR3_CLK #diff 1.5V AG17/AH17
set_property PACKAGE_PIN H6AG17 [get_ports {SI_MGT115SI5338_0_DDR3_CLK_clk_p}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {SI5338_0_clk_p[0]}]
DDR3_CLK_clk_p}]
##SI5338_1_MGTCLK_5338_C #diff MGT 1.8V AB6/AB5
set_property PACKAGE_PIN G22AB6 [get_ports {SI_FCLKSI5338_1_MGTCLK_5338_C_clk_p[10]}]
set_property PACKAGE_PIN D23 [get_ports {SI_FCLK_clk_p[2]}]###SI5338_3_LMK_CLK #diff MGT 1.8V to LMK CLKin1
##SI5338_4_MGTCLK2_5338_C #diff MGT 1.8V H6/H5
set_property PACKAGE_PIN G24H6 [get_ports {SI_FCLKSI5338_4_MGTCLK2_5338_C_clk_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {SI_FCLK_*}]

#----------
# FEX0##LMK_0_CLK_SYNTH_DCLKout0 #diff  1.8V AD29/AE29
set_property PACKAGE_PIN B20AD29 [get_ports {PCI_PERSTNLMK_0_CLK_SYNTH_DCLKout0_clk_p[0]}]
set_property IOSTANDARD LVCMOS18LVDS [get_ports {PCI_PERSTN}]
#----------
set_property PACKAGE_PIN K6 [get_ports {CLK_PCIe_100MHzLMK_0_CLK_SYNTH_DCLKout0_clk_p[0]}]
set_property PACKAGEDIFF_PINTERM N4TRUE [get_ports {pcie_7x_mgt_rxp[2LMK_0_CLK_SYNTH_DCLKout0_clk_p[0]}]
##LMK_1_CLK_SYNTH_DCLKout1 #diff  1.8V AE31/AF31
set_property PACKAGE_PIN R4AE31 [get_ports {pcie_7x_mgt_rxp[3LMK_1_CLK_SYNTH_DCLKout1_clk_p[0]}]
set_property PACKAGE_PINIOSTANDARD L4LVDS [get_ports {pcie_7x_mgt_rxp[1LMK_1_CLK_SYNTH_DCLKout1_clk_p[0]}]
set_property PACKAGEDIFF_PINTERM J4TRUE [get_ports {pcie_7x_mgt_rxpLMK_1_CLK_SYNTH_DCLKout1_clk_p[0]}]

PCB REV01:

#----------
#CLK DDR3
#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
set_property PACKAGE_PIN AC9 [get_ports CLK_DDR3_200MHz_clk_p]
set_property PACKAGE_PIN AD9 [get_ports CLK_DDR3_200MHz_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_n]

PCB REV02:

#----------
#CLK DDR3
#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
set_property PACKAGE_PIN AB11 [get_ports CLK_DDR3_200MHz_clk_p]
set_property PACKAGE_PIN AC11 [get_ports CLK_DDR3_200MHz_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_n]
###LMK_2_CLKIN_5338_P #diff  1.8Vto Si5338 IN1/IN2
###LMK_3_CLK_SYNTH_SDCLKout3 #diff  1.8Vto N.C.
###LMK_4_CLK_SYNTH_SDCLKout4 #diff MGT 1.8V T6/T5
###LMK_5_CLK_SYNTH_SDCLKout5 #diff  1.8Vto N.C.
###LMK_6_CLK_SYNTH_SDCLKout6 #diff  1.8Vto N.C.
###LMK_7_CLK_SYNTH_SDCLKout7 #diff MGT 1.8V F6/F5
###LMK_8_CLK_SYNTH_SDCLKout8 #diff  1.8Vto N.C.
###LMK_9_CLK_SYNTH_SDCLKout9 #diff  1.8Vto N.C.
###LMK_10_CLK_SYNTH_SDCLKout10 #diff  1.8Vto N.C.
###LMK_11_CLK_SYNTH_SDCLKout11 #diff  1.8Vto N.C.
###LMK_12_CLK_SYNTH_SDCLKout12 #diff  1.8Vto N.C.
###LMK_13_CLK_SYNTH_SDCLKout13 #diff  1.8Vto N.C.




#----------

Software Design - SDK/HSI

...

Template location: ./sw_lib/sw_apps/

hello_

...

tec0330

• Xiline Hello World as endless loop

...

scu

• Si5338 I2C Configuration example onlyvia MCS.

srec_spi_bootloader

• modified Xilinx SREC Bootloader, including SI5338 configurationBootloade
  

  • modified Files: blconfig

  • modified Files: blconfig.h, bootloader.c

  • add Files: si5338.h, si5338bootloader.c, register_map.h

  • modified  xilisf_v5_11: xilisf.mld (default Flash Typ:5)

...

...