Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Basic Notes
- export PDF to download, if vivado revision is changed!
- Template is for different design and SDSoC and examples, remove unused or wrong description!
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
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Table of contents
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Overview
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General Design description
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Design example with Linux and MGT-CLK frequency monitoring over VIO.
Key Features
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Excerpt
PetaLinux
SD
ETH
USB
I2C
PCIe
DP
FMeter
LED
Modified FSBL for SI5338 and SI5345 programming
Special FSBL for QSPI programming
Revision History
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initial release
Release Notes and Know Issues
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Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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reduced DDR speed for ES Variant
Xilinx has stopped ES1 support with 2018.2, please use 2017.1 reference design
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Additional HW Requirements:
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Content
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For general structure and of the reference design, see Project Delivery
Design Sources
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template (note: inner scroll ignore/only only with drawIO object):
Scroll Title
anchor
Figure_xyz
title
Text
Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use
Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed
Table template:
Layout macro can be use for landscape of large tables
Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux
<design name>/os/petalinux
PetaLinux template with current configuration
Additional Sources
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Additional design sources
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Type
Location
Notes
SI5338
<design name>/misc/Si5338
SI5338 Project with current PLL Configuration
SI5345
<design name>/misc/Si5345
SI5345 Project with current PLL Configuration
init.sh
<design name>/misc/init_script
Additional Initialization Script for Linux
Prebuilt
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Notes :
prebuilt files
Template Table:
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Prebuilt files
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File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIN-File
*.bin
Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image
*.img
Debian Image for SD-Card
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.hdf
Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
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Prebuilt files (only on ZIP with prebult content)
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File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIN-File
*.bin
Flash Configuration File with Boot-Image (Zynq-
Additional Sources
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Prebuilt
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<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
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File
...
File-Extension
...
Description
...
FPGAs)
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.hdf
Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example
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Basic Design Steps
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Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.
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_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter for minimum setup
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project
Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" Note: Select correct one, see TE Board Part Files
Create HDF and export to prebuilt folder
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Create Linux (uboot.elf and image.ub) with exported HDF
HDF is exported to "prebuilt\hardware\<short name>" Note: HW Export from Vivado GUI create another path as default workspace.
Use TE Template from /os/petalinux Note: run init_config.sh before you start petalinuxconfig. This will set correct temporary path variable.
Add Linux files (uboot.elf and image.ub) to prebuilt folder
"prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>" Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
Generate Programming Files with HSI/SDK
Run on Vivado TCL: TE::sw_run_hsi Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk Note: See SDK Projects
Launch
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Programming and Startup procedure
Programming
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Note
Check Module and Carrier TRMs for proper HW
Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.
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Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup Optional "TE::pr_program_flash_binfile -swapp hello_te0803teb0911" possible
Copy image.ub and optional misc/sd/init.sh on SD-Card
For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
Insert SD-Card
SD
Copy image.uband , Boot.bin and misc/sd/init.sh on SD-Card.
For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console: Note: Wait until Linux boot finished For Linux Login use:
User Name: root
Password: root
You can use Linux shell now.
I2C 0 Bus type: i2cdetect -y -r 0
ETH0 works with udhcpc
USB type "lsusb" or connect USB device
PCIe type "lspci"
Vivado HW Manager
(coming soon)
System Design - Vivado
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Block Design
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Activated interfaces:
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Note:
Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
add controllable IOs with short notes..
Monitoring:
add short notes for signals which will be monitored only
SI5338_CLK0 Counter:
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
Control:
User LED Control (D16, D15)
Monitoring:
MGT CLK Measurement:
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
Open "/misc/SI5345/Si5345-RevB-0808-02A-Project.slabtimeproj"
Modify settings
Export → Register File → select C code header → save to file
Replace Header files from FSBL template with generated file
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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};
Kernel
Deactivate:
CONFIG_CPU_IDLE (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ (only needed to fix JTAG Debug issue)
Rootfs
Activate:
i2c-tools
Applications
startup
Script App to load init.sh from SD Card if available.
General documentation how you work with these project will be available on Si5345
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
Add new row below first
Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
Metadata is only used of compatibility of older exports