Page properties |
---|
|
Template Revision 2.1 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
HTML |
---|
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
Page properties |
---|
|
Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
|
Scroll pdf ignore |
---|
Table of contents |
Overview
Zynq PS Design with Linux Example.
Refer to http://trenz.org/te0726-info for the current online version of this manual and other available documentation.
Key Features
Page properties |
---|
|
Notes : - Add basic key futures, which can be tested with the design
|
Excerpt |
---|
- VIDEO/AUDIO
- HDMI
- PetaLinux
- SD
- ETH
- USB
- I2C
- Special FSBL for QSPI programming
|
Revision History
Page properties |
---|
|
Notes : - add every update file on the download
- add design changes on description
|
Scroll Title |
---|
anchor | Table_DRH |
---|
title | Design Revision History |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Vivado | Project Built | Authors | Description |
---|
2018-10-31 | |
| Oleksandr Kiyenko | |
|
Release Notes and Know Issues
Page properties |
---|
|
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
|
Scroll Title |
---|
anchor | Table_KI |
---|
title | Known Issues |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Issues | Description | Workaround | To be fixed version |
---|
No known issues | --- | --- | --- |
|
Requirements
Software
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Scroll Title |
---|
anchor | Table_SW |
---|
title | Software |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Software | Version | Note |
---|
Vivado | 2018.2 | needed | SDK | 2018.2 | needed | PetaLinux | 2018.2 | needed |
|
Hardware
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Scroll Title |
---|
anchor | Table_HWM |
---|
title | Hardware Modules |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
---|
te0726-01 | 01 | REV01 | 64MB LPDDR2 | 16MB |
| not included, user modifications are needed | te0726-03r | r | REV02, REV03 | 128MB DDR3L | 16MB |
| not included, user modifications are needed | te0726-03m | m | REV02, REV03 | 512MB DDR3L | 16MB |
|
| te0726-03-07s-1c | 7s | REV03 | 512MB DDR3L | 16MB |
|
|
|
Design supports following carriers:
Scroll Title |
---|
anchor | Table_HWC |
---|
title | Hardware Carrier |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
|
Additional HW Requirements:
Scroll Title |
---|
anchor | Table_AHW |
---|
title | Additional Hardware |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Additional Hardware | Notes |
---|
USB Power | Use USB2.0 or higher for power supply via USB | USB Cable | Connect to USB2 or better USB3 Hub for proper power supply over USB | headphones |
|
|
Content
Page properties |
---|
|
Notes : - the content of the zip file
|
For general structure and of the reference design, see Project Delivery
Design Sources
Scroll Title |
---|
anchor | Table_DS |
---|
title | Design sources |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Type | Location | Notes |
---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration | SDSoC | <design name>/../SDSoC_PFM | SDSoC Platform will be generated by TE Scripts or as separate download |
|
Additional Sources
Scroll Title |
---|
anchor | Table_ADS |
---|
title | Additional design sources |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Type | Location | Notes |
---|
init.sh | <design name>/misc/init_script | Additional Initialization Script for Linux |
|
Prebuilt
Page properties |
---|
|
Notes : - prebuilt files
- Template Table:
Scroll Title |
---|
anchor | Table_PF |
---|
title | Prebuilt files |
---|
| Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
File | File-Extension | Description |
---|
BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
|
|
Scroll Title |
---|
anchor | Table_PF |
---|
title | Prebuilt files (only on ZIP with prebult content) |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
File | File-Extension | Description |
---|
BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
|
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- For 128MB and 64MB only:Netboot Offset must be reduced manually, see Config
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
Launch
Page properties |
---|
|
Note: - Programming and Startup procedure
|
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
- Connect JTAG and power on the carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0726" possible - Copy image.ub on SD-Card
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Copy ffmpeg compatible video or aplay compatible audio file on SD
- Insert SD-Card
SD
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (u-boot)
JTAG
Not used on this Example.
Usage
- Prepare HW like described in section Programming
- Connect UART USB (most cases same as JTAG)
- Insert SD Card with image.ub
- Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads U-boot from QSPI into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use a Linux shell now.
- I2C 1 Bus type: i2cdetect -y -r 5
Bus 0...5 possible - ETH0 works with udhcpc
- USB: insert USB device
- Start Video with "play <video file>
- "play" is alias to ffmpeg with some parameters for video and audio, type "alias" to see configuration
- for videos with higher resolution, disable audio on ffmpeg configuration
- Start Audio with "aplay <audio files
System Design - Vivado
Block Design
Scroll Title |
---|
anchor | Figure_BD |
---|
title | Block Design |
---|
|
|
PS Interfaces
Activated interfaces:
Scroll Title |
---|
anchor | Table_PSI |
---|
title | PS Interfaces |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Type | Note |
---|
DDR | --- | QSPI | MIO | USB0 | MIO, ETH over USB | SD1 | MIO | UART1 | MIO | I2C0 | EMIO | I2C1 | MIO | GPIO | MIO / EMIO | USB RST | MIO | TTC0..1 | MIO | WDT | MIO | AXI HP0..1 |
| DMA0..1 |
|
|
Constraints
Basic module constraints
Code Block |
---|
language | ruby |
---|
title | _i_bitgen_common.xdc |
---|
|
#
# Common BITGEN related settings for TE0726
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constraint
Code Block |
---|
language | ruby |
---|
title | _i_common.xdc |
---|
|
#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Code Block |
---|
language | ruby |
---|
title | _i_te0726.xdc |
---|
|
#set_property IOSTANDARD LVCMOS33 [get_ports spdif_tx_o]
#set_property PACKAGE_PIN K15 [get_ports spdif_tx_o]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_1_tri_io[*]}]
# GPIO Pins
# GPIO2
set_property PACKAGE_PIN K15 [get_ports {GPIO_1_tri_io[0]}]
# GPIO3
set_property PACKAGE_PIN J14 [get_ports {GPIO_1_tri_io[1]}]
# GPIO4
set_property PACKAGE_PIN H12 [get_ports {GPIO_1_tri_io[2]}]
# GPIO5
set_property PACKAGE_PIN N14 [get_ports {GPIO_1_tri_io[3]}]
# GPIO6
set_property PACKAGE_PIN R15 [get_ports {GPIO_1_tri_io[4]}]
# GPIO7
set_property PACKAGE_PIN L14 [get_ports {GPIO_1_tri_io[5]}]
# GPIO8
set_property PACKAGE_PIN L15 [get_ports {GPIO_1_tri_io[6]}]
# GPIO9
set_property PACKAGE_PIN J13 [get_ports {GPIO_1_tri_io[7]}]
# GPIO10
set_property PACKAGE_PIN H14 [get_ports {GPIO_1_tri_io[8]}]
# GPIO11
set_property PACKAGE_PIN J15 [get_ports {GPIO_1_tri_io[9]}]
# GPIO12
set_property PACKAGE_PIN M15 [get_ports {GPIO_1_tri_io[10]}]
# GPIO13
set_property PACKAGE_PIN R13 [get_ports {GPIO_1_tri_io[11]}]
# GPIO16
set_property PACKAGE_PIN L13 [get_ports {GPIO_1_tri_io[12]}]
# GPIO17
set_property PACKAGE_PIN G11 [get_ports {GPIO_1_tri_io[13]}]
# GPIO18
set_property PACKAGE_PIN H11 [get_ports {GPIO_1_tri_io[14]}]
# GPIO19
set_property PACKAGE_PIN R12 [get_ports {GPIO_1_tri_io[15]}]
# GPIO20
set_property PACKAGE_PIN M14 [get_ports {GPIO_1_tri_io[16]}]
# GPIO21
set_property PACKAGE_PIN P15 [get_ports {GPIO_1_tri_io[17]}]
# GPIO22
set_property PACKAGE_PIN H13 [get_ports {GPIO_1_tri_io[18]}]
# GPIO23
set_property PACKAGE_PIN J11 [get_ports {GPIO_1_tri_io[19]}]
# GPIO24
set_property PACKAGE_PIN K11 [get_ports {GPIO_1_tri_io[20]}]
# GPIO25
set_property PACKAGE_PIN K13 [get_ports {GPIO_1_tri_io[21]}]
# GPIO26
set_property PACKAGE_PIN L12 [get_ports {GPIO_1_tri_io[22]}]
# GPIO27
set_property PACKAGE_PIN G12 [get_ports {GPIO_1_tri_io[23]}]
## DSI_D0_N
#set_property PACKAGE_PIN F13 [get_ports {GPIO_1_tri_io[24]}]
## DSI_D0_P
#set_property PACKAGE_PIN F14 [get_ports {GPIO_1_tri_io[25]}]
## DSI_D1_N
#set_property PACKAGE_PIN F12 [get_ports {GPIO_1_tri_io[26]}]
## DSI_D1_P
#set_property PACKAGE_PIN E13 [get_ports {GPIO_1_tri_io[27]}]
## DSI_C_N
#set_property PACKAGE_PIN E11 [get_ports {GPIO_1_tri_io[28]}]
## DSI_C_P
#set_property PACKAGE_PIN E12 [get_ports {GPIO_1_tri_io[29]}]
## CSI_D0_N
#set_property PACKAGE_PIN M11 [get_ports {GPIO_1_tri_io[30]}]
## CSI_D0_P
#set_property PACKAGE_PIN M10 [get_ports {GPIO_1_tri_io[31]}]
## CSI_D1_N
#set_property PACKAGE_PIN P14 [get_ports {GPIO_1_tri_io[32]}]
## CSI_D2_P
#set_property PACKAGE_PIN P13 [get_ports {GPIO_1_tri_io[33]}]
## CSI_C_N
#set_property PACKAGE_PIN N12 [get_ports {GPIO_1_tri_io[34]}]
## CSI_C_P
#set_property PACKAGE_PIN N11 [get_ports {GPIO_1_tri_io[35]}]
## PWM_R
##set_property PACKAGE_PIN N8 [get_ports {GPIO_1_tri_io[36]}]
## PWM_L
##set_property PACKAGE_PIN N7 [get_ports {GPIO_1_tri_io[37]}]
# PWM_R
set_property PACKAGE_PIN N8 [get_ports PWM_R]
# PWM_L
set_property PACKAGE_PIN N7 [get_ports PWM_L]
set_property IOSTANDARD LVCMOS33 [get_ports PWM_*]
|
Code Block |
---|
language | ruby |
---|
title | _i_hdmi.xdc |
---|
|
set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p]
set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[*]}]
set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}]
set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}]
set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}]
|
Code Block |
---|
language | ruby |
---|
title | _i_csi.xdc |
---|
|
set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p]
set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}]
set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}]
set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}]
set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}]
set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}]
# RPI Camera 1
create_clock -period 6.250 -name csi_clk -add [get_ports csi_c_clk_p]
# RPI Camera 2.1
#create_clock -period 1.875 -name csi_clk -add [get_ports csi_c_clk_p]
|
Code Block |
---|
language | ruby |
---|
title | _i_timing.xdc |
---|
|
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/tx_sync/out_data_reg[4]}]
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/SDATA_O_reg[0]}]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_3]
set_false_path -from [get_clocks clk_fpga_3] -to [get_clocks clk_fpga_0]
set_false_path -from [get_pins {zsys_i/axi_reg32_0/U0/axi_reg32_v1_0_S_AXI_inst/slv_reg16_reg[1]/C}] -to [get_pins zsys_i/video_in/axis_raw_demosaic_0/U0/colors_mode_i_reg/D]
set_false_path -from [get_pins zsys_i/video_in/csi_to_axis_0/U0/lane_align_inst/err_req_reg/C] -to [get_pins zsys_i/video_in/csi2_d_phy_rx_0/U0/clock_upd_req_reg/D]
set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_max_first_increment_reg[2]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]
set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]
|
Software Design - SDK/HSI
HTML |
---|
<!--
optional chapter
separate sections for different apps
--> |
For SDK project creation, follow instructions from:
SDK Projects
Application
SDK template in ./sw_lib/sw_apps/ available.
zynq_fsbl
TE modified 2018.2 FSBL
- Changes:
- enable VTC and VDMA cores (fsbl_hooks.c)
zynq_fsbl_flash
TE modified 2018.2 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialization
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
hello_te0726
Hello TE0726 is a Xilinx Hello World example as an endless loop instead of one console output and TE FSBL screen on HDMI Monitor.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
For 64MB variant only:
- CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x2000000
For 128MB variant only:
- CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x4000000
U-Boot
No changes.
Device Tree
Code Block |
---|
|
/include/ "system-conf.dtsi"
/ {
};
/ {
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
hdmi_fb_reserved_region@1FC00000 {
compatible = "removed-dma-pool";
no-map;
// 512M (M modules)
reg = <0x1FC00000 0x400000>;
// 128M (R modules)
//reg = <0x7C00000 0x400000>;
};
camera_fb_reserved_region@1F800000 {
compatible = "removed-dma-pool";
no-map;
// 512M (M modules)
reg = <0x1F800000 0x400000>;
// 128M (R modules)
//reg = <0x7800000 0x400000>;
};
};
hdmi_fb: framebuffer@0x1FC00000 { // HDMI out
compatible = "simple-framebuffer";
// 512M (M modules)
reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p
// 128M (R modules)
//reg = <0x7C00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
status = "okay";
};
camera_fb: framebuffer@0x1F800000 { // CAMERA in
compatible = "simple-framebuffer";
// 512M (M modules)
reg = <0x1F800000 (1280 * 720 * 4)>; // 720p
// 128M (R modules)
//reg = <0x7800000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
};
vcc_3V3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vccaux-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
partition@0x00000000 {
label = "boot";
reg = <0x00000000 0x00500000>;
};
partition@0x00500000 {
label = "bootenv";
reg = <0x00500000 0x00020000>;
};
partition@0x00520000 {
label = "kernel";
reg = <0x00520000 0x00a80000>;
};
partition@0x00fa0000 {
label = "spare";
reg = <0x00fa0000 0x00000000>;
};
};
};
/*
* We need to disable Linux VDMA driver as VDMA
* already configured in FSBL
*/
&video_in_axi_vdma_0 {
status = "disabled";
};
&video_out_axi_vdma_0 {
status = "disabled";
};
&video_out_v_tc_0 {
//xilinx-vtc: probe of 43c20000.v_tc failed with error -2
status = "disabled";
};
&gpio0 {
interrupt-controller;
#interrupt-cells = <2>;
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
i2cmux0: i2cmux@70 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c1@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
id_eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
};
i2c1@1 { // Display Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c1@2 { // HDMI Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c1@3 { // Camera Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
usb-phy = <&usb_phy0>;
} ;
/*
* Sound configuration
*/
/{
// Custom driver based on spdif-transmitter
te_audio: dummy_codec_te {
compatible = "te,te-audio";
#sound-dai-cells = <0>;
};
// Simple Audio Card from AXI_I2S and custom XADC audio input and
// PWM audio output cores
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "TE0726-PWM-Audio";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "In Jack",
"Line", "Line In Jack",
"Line", "Line Out Jack",
"Headphone", "Out Jack";
simple-audio-card,routing =
"Out Jack", "te-out",
"te-in", "In Jack";
simple-audio-card,cpu {
sound-dai = <&audio_axi_i2s_adi_0>;
};
simple-audio-card,codec {
sound-dai = <&te_audio>;
};
};
};
&audio_axi_i2s_adi_0 {
compatible = "adi,axi-i2s-1.00.a";
reg = <0x43c00000 0x1000>;
clocks = <&clkc 15>, <&clkc 18>; // FCLK_CLK0, FCLK_CLK3
clock-names = "axi", "ref";
dmas = <&dmac_s 0 &dmac_s 1>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
};
/*
* We need to disable Linux XADC driver to use XADC for audio recording
*/
&adc {
status = "disabled";
};
|
Kernel
Activate:
- CONFIG_XILINX_GMII2RGMII
- CONFIG_USB_USBNET
- CONFIG_USB_NET_SMSC95XX
- CONFIG_USBIP_CORE
- CONFIG_FB_SIMPLE
- CONFIG_SND_SIMPLE_CARD
- CONFIG_SND_SOC_ADI_AXI_I2S
Deactivate:
Rootfs
Activate:
- i2c-tools
- alsa-plugins
- alsa-lib-dev
- libasound
- alsa-conf-base
- alsa-conf
- alsa-utils
- alsa-utils-aplay
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Add on new project:
- petalinux-create -t apps -n startup --enable
- copy/create startup app files
rpicam
Application used to enable and configure Raspbery Pi camera module
See: \os\petalinux\project-spec\meta-user\recipes-apps\rpicam\files
Add on new project:
- petalinux-create -t apps -n rpicam --enable
- copy/create rpicam app files
Kernel Modules
te-audio-codec
Simple module stab to use audio interface.
See: \os\petalinux\project-spec\meta-user\recipes-modules\te-audio-codec\files
Add on new project:
- petalinux-create -t modules -n te-audio-codec --enable
- copy/create te-audio-codec module files
Core base files
profile
Simple profile for alias
See: \project-spec\meta-user\recipes-core\base-files\files\profile
Add on new project:
Additional Software
Page properties |
---|
|
Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
|
No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties |
---|
|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Scroll Title |
---|
anchor | Table_dch |
---|
title | Document change history. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | 2*,*,3*,4* |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Document Revision | Authors | Description |
---|
Page info |
---|
| modified-date |
---|
| modified-date |
---|
dateFormat | yyyy-MM-dd |
---|
|
| Page info |
---|
infoType | Current version |
---|
dateFormat | yyyy-MM-dd |
---|
prefix | v. |
---|
type | Flat |
---|
|
| Page info |
---|
infoType | Modified by |
---|
dateFormat | yyyy-MM-dd |
---|
type | Flat |
---|
|
| | -- | all | Page info |
---|
infoType | Modified users |
---|
dateFormat | yyyy-MM-dd |
---|
type | Flat |
---|
|
| -- |
|
Legal Notices
Include Page |
---|
| IN:Legal Notices |
---|
| IN:Legal Notices |
---|
|