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Intel MAX 10 10M08 FPGA SoC
- 8 MByte SDRAM
8 MByte QSPI Flash memory
- Onboard oscillator with 3 selectable frequencies
- Analog Devices ADXL362 MEMS 3-axis accelerometer
- Analog Devices ADT7320 temperature sensor
- Analog Devices ADPD188BI smoke detector
- Analog Devices AD5592R ADC/DAC
- JTAG and UART over Micro USB2 connector
- 1x6 pin header for JTAG access to FPGA SoC
- 1x PMOD header providing 8 GPIOsI/O
2x 14-pin headers (2,54 mm pitch) providing 22 GPIOs I/O with 7 analog inputs as alternative function
- 1x 3-pin header providing 2 analog inputs or 1 GPIOdigital I/O
8x user LEDs
- 1x user push button
- 5.0V single power supply with on-board voltage regulators
- Size: 61.5 x 25 mm
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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Storage device name | Content | Notes |
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| Quad SPI Flash, U5 | DEMO DesignEmpty | - | | FTDI chip configuration EEPROM, U9 | Programmed- | Arrow Blaster identification |
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Control Signals
| Page properties |
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- Overview of Boot Mode, Reset, Enables,
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| Scroll Title |
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| anchor | Table_OV_CS |
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| title | Control Signals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Control signal | Switch / Button / LED / Pin | Signal Schematic Names | Connected to | Functionality | Notes |
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| MAX10 FPGA U1 JTAGEN | header J4, pin 2 | JTAGEN | MAX10 FPGA U1, bank 1B, pin E5 | high or floating: MAX 10 JTAG enabled,
floatinglow: MAX 10 JTAG disabled | switch the JTAG pins to user GPIO's if drive this pin to GNDI/O if pin is driven low | | MAX10 FPGA U1 Reset | header J2, pin 10 | RESET | MAX10 FPGA U1, bank 8, pin E7 | low active reset line | also connected to Reset push button S1 | | Supply voltage indicator | Green LED D1 | 3.3V | DC-DC converter U4 | indicating 3.3V voltage level | - | | Configuration DONE indicator | Red LED D10 | CONF_DONE | MAX10 FPGA U1, bank 8, pin C5 | indicating FPGA configuration completed | OFF: configuration completed, ON: FPGA not configured | | Reset Push button | S1 | RESET | MAX10 FPGA U1, bank 8, pin E7 | low active logic | - | | User Push button | S2 | USER_BTN | MAX10 FPGA U1, bank 8, pin E6 | low active logic | available to user |
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the MAX10 non-volatile CFM memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means SRAM (using a SOF file), then the configuration is lost after power off.
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| Scroll Title |
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| anchor | Table_SIP_JTAG |
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| title | Optional JTAG pin header |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| JTAG Signal | Pin on Header J4 | Note |
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| TCK | 3 | - | | TDI | 5 | - | | TDO | 4 | - | | TMS | 6 | - | | JTAGEN | 2 | leave floating when use JTAG interface, otherwise signals on FPGA are GPIOsopen for normal operation |
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Micro-USB2 Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
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| Scroll Title |
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| anchor | Table_SIP_FPGA-bank-I/O's |
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| title | General overview of single ended FPGA bank I/O's |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Bank | I/O's Count | Connected to | Notes |
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| 2 | 4 | 1x14 pin header, J1 | user GPIO's | | 8 | Pmod connector, J6 | user GPIO's | | 1 | clock oscillator, U7 | 12.0000 MHz reference clock input | | 1 | clock oscillator, U10 | reference clock input from adjustable optional oscillator U10 | | 1 | accelerometer IC, U11 | interrupt 1 line of Analog Devices MEMS accelerometer | | 5 | 9 | 1x14 pin header, J2 | 2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same bank and 1 I/O (D11_R) of bank 6 | | 1 | accelerometer IC, U11 | interrupt 2 line of Analog Devices MEMS accelerometer | | 1 | clock oscillator, U10 | control line to adjust oscillator with three frequencies of clock outputselect adjustable oscillator output frequency | | 1 | temperature sensor IC, U8 | interrupt line of temperature thresholds | | 6 | 18 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface | | 3 | 22 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface | | 3 | SPI interface connected to IC U8, U11, U12 | SPI interface (MISO, MOSI, MCLK) for temperature sensor U8, 3-axis accelerometer U11 and ADC/DAC U12 | | 1 | temperature sensor IC, U8 | chip-select line for SPI interface | | 1 | accelerometer IC, U11 | chip-select line for SPI interface | | 1 | ADC/DAC IC , U12 | data input frame synchronization line of ACD/DAC IC (active low control input) | | 1 | temperature sensor IC, U8 | interrupt line of critical temperature | | 1A | 8 | smoke detector IC, U14 | SPI, I²C interface and GPIO's of smoke detector IC U14 | | 1B | 1 | pin headers header J3 | 1 x GPIOdigital I/O | | 5 | FTDI FT2232H IC U3 (4 JTAG I/O's) and pin header J4 (5 I/O's) | 4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's I/O if drive this pin to GND | | 8 | 8 | LEDs D2 ... D9 | Red user LEDs | | 6 | QSPI Flash memory, U5 | 6 pins Quad SPI interface , 2 of them pulled up as configuration pins during initialization(2 pins have are shared function) | | 6 | FTDI FT2232H JTAG/UART adapter, U3 | 6 pins configurable as GPIO /or UART or other serial interfaces | | 1 | Red LED, D10 | Configuration DONE Led (ON when configuration in progress, OFF when configuration is done) | | 1 | User button S2 | user configurable | | 1 | Reset button S1 and pin J2-10 | low active reset line for FPGA reconfiguration |
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Channel B is routed via 6 I/O's to bank 8 of MAX10 FPGA U1 and are usable as FIFOUART, GPIO, UART or other standard interfacesSPI or bit-banged I2C.
| Scroll Title |
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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| Pin 12, ADBUS0 | TCK | FPGA bank 1B, pin G2
| JTAG interface | | Pin 13, ADBUS1 | TDI | FPGA bank 1B, pin F5 | | Pin 14, ADBUS2 | TDO | FPGA bank 1B, pin F6 | | Pin 15, ADBUS3 | TMS | FPGA bank 1B, pin G1 | | Pin 32, BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable | | Pin 33, BDBUS1 | BDBUS1 | FPGA bank 8, pin B4
| user configurable | | Pin 34, BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable | | Pin 35, BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable | | Pin 37, BDBUS4 | BDBUS4 | FPGA bank 8, pin B6
| user configurable | | Pin 38, BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
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