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Default Clock PLL Frequencies
PLL Out | Freq | I/O Standard | Connected to |
---|---|---|---|
0 | 100 | LVDS | FPGA bank 2A |
1 | 100 | LVDS | B2B Connector |
2 | 100 | CMOS | B2B Connector |
3 | B2B Connector | ||
4 | B2B Connector | ||
5 | 133.3333 | LVDS | DDR3 EMIF |
6 | 100 | GBT 1D | |
7 | 125 | GBT 1D | |
8 | 100 | GBT 1C | |
9 | 125 | GBT 1C |
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