...
Page properties |
---|
|
The input power supply must be mentioned. Add Link to overview picture with connector label.
|
Label | Designator | Power | Description |
---|
Overview - 12 | J20 | 12V and 5V | Recommended power supply unit is PC power supply unit:- DIP S4-4 can be switched OFF with this power supply configuration (CPLD firmware depended)
|
Overview - 4 | J25 | 12V | Optional single 12V power supply: DIP S4-4 must be switched ON with this power supply |
Current depends manly on design and cooling solution. Use Xilinx Power Estimator and/or Your Vivado Project to estimate min current. Minimum of 3A are recommanded for basic functionality.
...
Page properties |
---|
|
Explain all user LEDs functionality and connections. Add Link to overview picture with connector label.
|
LEDs used different Blink Sequence to indicate all state:
Scroll Title |
---|
anchor | Table_LED_SEQ |
---|
title | Carrier LEDs LED Sequencing (CPLD Firmware depended) |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
LabelDesignator6 | PJTAG Boot | Color | Usage | Description | Overview - 2 | D7 | Red | status | Priority | Description | Blink sequencing |
---|
1 | PS POR Reset pressed long time (or whole system is powered off) | ON | 2 | PS Soft Reset pressed short time | OFF | 3 | SD Boot | *ooooooo | 4 | QSPI Boot | **oooooo | 5 | eMMC Boot | ***ooooo | Note |
---|
******** (slow blinking) | ~0,7 Hz | continuous blinking, like SFP LEDs or Enclosure HD LED when board is powered down | ******** (fast blinking) | ~5,8 Hz | continuous blinking, like D6 LED or Enclosure Power LED when board is powered down | *****ooo | ~0,7 Hz, duty cycle 5/8 | 5 times fast blink with a break | JTAG BootHz, duty cycle 4/8 | 4 times fast blink with a break | *** | **ooo8 | Error | ******** (fast blinking) | Overview - 2 | D6 | Green | status | Priority | Description | Blink sequencing |
---|
1 | Power OFF | ******** (fast blinking) | 2 | PG_LPD low | *****ooo | 3 | PG_FPD low | ****oooo | 4 | PG_PL low | ***ooooo | 5 | PG_DDR low or PG_PSGT low or PG_PLL low or PG_GT_L low or PG_GT_R low | **oooooo | 6 | POK_1V8 low or POK_FMC low or perihpery_pg low or (Main Power State Machine Ready and FMC Sanity check low) | *ooooooo | 7 | Main Power State Machine Ready | OFF | 8 | ERROR some power failed, see XMOD LEDs | ON |
ooooo | ~0,7 Hz, duty cycle 3/8 | 3 times fast blink with a break | **oooooo | ~0,7 Hz, duty cycle 2/8 | 2 times fast blink with a break | *ooooooo | ~0,7 Hz, duty cycle 1/8 | 1 times fast blink with a break | ON | --- | LED ON | OFF | --- | LED OFF |
|
Scroll Title |
---|
anchor | Table_LED |
---|
title | Carrier LEDs (CPLD Firmware depended) |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Overview - 6 | J10 Power LED | Blue (symbol light bulb) | status/user |
Priority | Description | Blink sequencing |
---|
1 |
| power button PS POR Reset pressed long time |
| forced power down******** (fast blinking) | (or whole system is powered off) | ON | 2 | PS Soft Reset pressed short time | OFF | 3 | SD Boot | *ooooooo | 4 | QSPI Boot | **oooooo | 5 | eMMC Boot | ***ooooo | 6 | PJTAG Boot |
|
2 | Main Power State Machine Idle and Power of State**** (slow blinking)3 | power button pressed short time power to power on/off4 | PS reset button pressed long timeoooo5 | PS reset button pressed short time | ooooo6 | power down sequencing is running | **oooooo | 7 | whole system hold into reset | *ooooooo | 8 | MIO40 | User Defined | Overview - 6 | J10 HD LED | Red (symbol drive) | status/user | Priority | Description | Blink sequencing |
---|
1 |
| PS Init is lowPower OFF | ******** (fast blinking) | 2 |
| PS Error HighPS Error Status HighSOC Done SC0 | User Defined | Overview - 8 | XMOD1 D4 | Red | status | Priority | XMOD Button | Description | Blink sequencing |
---|
PG_DDR low or PG_PSGT low or PG_PLL low or PG_GT_L low or PG_GT_R low | **oooooo | 6 | POK_1V8 low or POK_FMC low or perihpery_pg low or ( |
|
1 | Pressed | Main Power State Machine Ready |
| , but failed******* (fast blinking)2 | Pressed | PS State Machine PS LPD ON/OFF | *ooooooo | 3 | Pressed | PS State Machine PS FPD ON/OFF | **oooooo | 4 | Pressed | PS State Machine PS DDR,GT,PLL ON/OFF | ***ooooo | 5 | Pressed | PL State Machine PL and PL GT ON/OFF | ****oooo | 6 | Pressed | PS Init low | ON | 1 | Unpressed | Main Power State Machine ATX ON/OFF | *ooooooo | 2 | Unpressed | Main Power State Machine 5V ON/OFF | **oooooo | 3 | Unpressed | Main Power State Machine Module ON/OFF | ***ooooo | 4 | Unpressed | Main Power State Machine 1.8V ON/OFF | ooooooo | 7 | Main Power State Machine Ready | OFF | 8 | ERROR some power failed, see XMOD LEDs | ON |
| Overview - 6 | J10 Power LED | Blue (symbol light bulb) | status/user |
Priority | Description | Blink sequencing |
---|
1 | power button pressed long time forced power down | ******** (fast blinking) | 2 | Main Power State Machine Idle and Power of State | ******** (slow blinking) | 3 | power button pressed short time power to power on/off | *****ooo | 4 | PS reset button pressed long time |
|
Unpressed | Main Power State Machine 3.3V and VADJ ON/OFF | PS reset button pressed short time | *** |
| **oooUnpressed | Main Power State Machine Wait Ready ON/OFF | ******** (fast blinking) | 7 | Unpressed | PS Init low | ON | 8 | Pressed/Unpressed | all fine | OFF | power down sequencing is running | **oooooo | 7 | whole system hold into reset | *ooooooo | 8 | MIO40 | User Defined |
| Overview - 6 | J10 HD LED | Red (symbol drive) |
Overview - 9 | XMOD2 D4 | Red | status/user |
Priority | Description | Blink sequencing |
---|
1 |
| Power On Reset slow Init high*** (fast blinking)ooo | 3 | PS Error Status High | ****oooo | 4 | SOC Done low | ***ooooo | 5 | SC0 |
|
3 | SC17 12SFP D1/user |
Priority | XMOD Button | Description | Blink sequencing |
---|
1 | Pressed |
| Power On ResetMain Power State Machine Ready, but FMC Sanity check failed | ******** ( |
| slow PS Init high | ******** (fast blinking) | 3 | RGPIO(0), when RGPIO Enabled over FPGA | User Defined | 4 | -- | OFF | PS State Machine PS LPD ON/OFF | *ooooooo | 3 | Pressed | PS State Machine PS FPD ON/OFF | **oooooo | 4 | Pressed | PS State Machine PS DDR,GT,PLL ON/OFF | ***ooooo | 5 | Pressed | PL State Machine PL and PL GT ON/OFF | ****oooo | 6 | Pressed | PS Init low | ON | 1 | Unpressed | Main Power State Machine ATX ON/OFF | *ooooooo | 2 | Unpressed | Main Power State Machine 5V ON/OFF | **oooooo | 3 | Unpressed | Main Power State Machine Module ON/OFF | ***ooooo | 4 | Unpressed | Main Power State Machine 1.8V ON/OFF | ****oooo | 5 | Unpressed | Main Power State Machine 3.3V and VADJ ON/OFF | *****ooo | 6 | Unpressed | Main Power State Machine Wait Ready ON/OFF |
|
Overview - 13 | SFP D8 | Green | status/user | Priority | Description | Blink sequencing |
---|
1 | Power On Reset | ******** (slow blinking) | 2 | PS Init high | ******** (fast blinking) | 3 | RGPIO(1), when RGPIO Enabled over FPGA | User Defined | 4 | -- | OFF |
Overview - 14 | SFP D9 | Red | status/user | Priority | Description | Blink sequencing |
---|
1 | Power On Resetslow 2 high******** (fast blinking) | 3 | RGPIO(2), when RGPIO Enabled over FPGA | User Defined | low | ON | x | Pressed/Unpressed | all fine |
|
4 | -- 15SFP D10GreenRed | status/user |
Priority | Description | Blink sequencing |
---|
1 | Power On Reset | ******** (slow blinking) | 2 | PS Init high | ******** (fast blinking) | 3 |
| RGPIO(3), when RGPIO Enabled over FPGA4 | -- | OFF 16ETH J7YellowRed | status/user |
Priority | Description | Blink sequencing |
---|
1 | Power On Reset | ******** (slow blinking) | 2 | PS Init high | ******** (fast blinking) | 3 |
|
ETH PHY LED | (not PHY_LED0) | RGPIO(0), when RGPIO Enabled over FPGA | User Defined | 4 | -- | OFF |
| Overview - 13 | SFP D8 | Green | status/user |
Overview - 17 | ETH J7 | Green/Orange | status |
Priority | Description | Blink sequencing |
---|
1 | Power On Reset | ******** (slow blinking) | 2 | PS Init high | ******** (fast blinking) | 3 |
|
ETH PHY LED | RGPIO(1), when RGPIO Enabled over FPGA | User Defined | 4 | -- | OFF |
| (PHY_LED1) 18D4GreenRed | status/user |
Priority | Description | Blink sequencing |
---|
1 |
|
1.8V disabled, inter CPLD RGPIO is disabled | fast 1.8V enabled, inter CPLD RGPIO is disabledooo3 | Power On Reset | *oooo4 | USB Reset | ***ooooo42), when RGPIO Enabled over FPGA | User Defined | 4 | -- |
| *ooooooo 18D5RedGreen | status/user |
Priority | Description | Blink sequencing |
---|
1 |
|
1.8V disabled, inter CPLD RGPIO is disabled | fast 1.8V enabled, inter CPLD RGPIO is disabledooo3 | Power On Reset | *oooo4 | PCie Reset | ***ooooo43), when RGPIO Enabled over FPGA | User Defined | 4 | -- | OFF |
| Overview - | *ooooooo |
Priority | Description | Blink sequencing |
---|
1 |
|
|
...
Furthermore, there are two user LEDs on module TE0728.
...
anchor | Table_LED |
---|
title | Module LEDs |
---|
Power On Reset | ******** (slow blinking) | 2 | PS Init high | ******** (fast blinking) | 3 | ETH PHY LED | (not PHY_LED0) |
| Overview - 17 | ETH J7 | Green/Orange | status |
Priority | Description | Blink sequencing |
---|
1 | Power On Reset | ******** (slow blinking) | 2 | PS Init high | ******** (fast blinking) | 3 | ETH PHY LED | (PHY_LED1) |
| Overview - 18 | D4 | Green | status/user |
Priority | Description | Blink sequencing |
---|
1 | 1.8V disabled, inter CPLD RGPIO is disabled | ******** (fast blinking) | 2 | 1.8V enabled, inter CPLD RGPIO is disabled | *****ooo | 3 | Power On Reset | ****oooo | 4 | USB Reset | ***ooooo | 5 | RGPIO(4), when RGPIO Enabled over FPGA | User Defined | 6 | all fine | *ooooooo |
| Overview - 18 | D5 | Red | status/user |
Priority | Description | Blink sequencing |
---|
1 | 1.8V disabled, inter CPLD RGPIO is disabled | ******** (fast blinking) | 2 | 1.8V enabled, inter CPLD RGPIO is disabled | *****ooo | 3 | Power On Reset | ****oooo | 4 | PCie Reset | ***ooooo | 5 | RGPIO(4), when RGPIO Enabled over FPGA | User Defined | 6 | all fine | *ooooooo |
|
|
Scroll Title |
---|
anchor | Table_LED |
---|
title | Module LEDs |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Label | Designator | Color | Connected to | Description |
---|
Overview - 10 | D1 | Red | DONE signal (PS Configuration Bank 503) | This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly. |
|
JTAG/UART
Page properties |
---|
|
Explain JTAG or UART connection . Add Link to overview picture with connector label.
|
Label | Designator | Description |
---|
Overview - 8 | J12 | - SoC JTAG/UART over USB, UART Speed depends on design, normally 15200
- XMOD with Xilinx Licence (green dot)
|
Overview - 9 | J28 | - CPLD or FMC JTAG over USB
- XMOD without Xilinx Licence
- Press Button to see Firmware ID over UART (need CPLD Firmware 7 or newer), UART Speed 115200
|
DIP Switch on bouth XMOD JTAG adapters must be set like on the following table.
Scroll Title |
---|
anchor | Table_XMOD_JTAG |
---|
title | XMOD JTAG DIP Switch. Attention: Never changes the default setting |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
XMOD DIP Switch | Setting |
---|
1 | ON | 2 | OFF | 3 | OFF | 4 | OFF |
|
For more information refer to TE0790.
CPLD Firmware
Firmware Update Instruction and CPLD
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
...
This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly.
JTAG/UART
Page properties |
---|
|
Explain JTAG or UART connection . Add Link to overview picture with connector label.
|
...
- SoC JTAG/UART over USB, UART Speed depends on design, normally 15200
- XMOD with Xilinx Licence (green dot)
...
- CPLD and FMC JTAG
- Press Button to see Firmware ID over UART (need CPLD Firmware 7 or newer), UART Speed 115200
DIP Switch on the XMOD JTAG adapter must be set like the following table.
...
anchor | Table_XMOD_JTAG |
---|
title | XMOD JTAG DIP Switch. Attention: Never changes the default setting |
---|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
...
For more information refer to TE0790.
CPLD Firmware
Firmware Update Instruction and CPLD description is available on TEBF0808 CPLD Firmware. Source code of the firmware is available on the download area of the TEBF0808.
...
Scroll Title |
---|
anchor | Table_CPLD_FIRM |
---|
title | CPLD Firmware and Statistic over UART |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Type | Description |
---|
TE0808-x_CPLD-REV07 | CPLD Firmware Version | MP | - Main Power State, Note: Only correct, if 1.8V is powered on
- First Number indicates 1.8V Power state(1-ON)
- Second Number indicates Main State Machine:
- 0:IDLE (Power OFF)
- 1:ATX ON/OFF
- 2:V5 ON/OFF
- 3:Module Power ON/OFF → (Different domains over LED visible)
- 4:1.8V ON/OFF
- 5:Periphery ON/OFF
- 6: Wait Ready (Power Ok, SoC on Reset)
- 7. Ready (Power/SoC OK)
| PIN | - PS Init, when Power Reset released
- First Number current PS-INIT (Inverted)
- Second Number PSINIT counter
| PEE | - PS ERROR, when Power Reset released
- First Number current PS-ERROR
- Second Number ERROR counter
| PES | - PS ERROR Status, when Power Reset released
- First Number current PS-ERROR Status
- Second Number ERROR Status counter
| PSR | - PS Soft Reset(also high, PS Power On Rese is active)
- First Number current PS-Soft Reset
- Second Number PS-Soft Reset counter
| PHR | - PS Power On Reset
- First Number current PS- Power On PS- Power On Reset
- Second Number PS- Power On Reset counter
| POR | - Main Power On Reset
- First Number current Main- Power On Reset
- Second Number Main Power On Reset counter
| USB | - USB Reset
- First Number current USB Reset
- Second Number PS- Power On Reset USB reset counter
| PORPCI | - Main Power On PCIe Reset
- First Number current Main- Power On PCIe Reset
- Second Number Main Power On Reset counter
| USB | - USB Reset
- First Number current USB Reset
- Second Number USB reset counter
| PCI | - PCIe Reset
- First Number current PCIe Reset
- Second Number PCIe reset counter
|
|
Reference Designs
Page properties |
---|
|
In this Section you must refer to the Reference Design (Test board) for the particular module. For Example: TE0728 Reference Designs |
...
Reference Designs
Page properties |
---|
|
In this Section you must refer to the Reference Design (Test board) for the particular module. For Example: TE0728 Reference Designs |
Link to different Reference Designs (Descriptions and Download)
It's recommended to use prebuilt Boot.bin and image.ub of newest Starterkit Reference Design for first test. Basic Steps:
- Power Supply over ATX, optional 12V power jack
- Download Reference Design
- Copy Boot.bin and image.ub on SD
- Connect USB to XMOD with Green Dot
- Open Putty
- Set Boot Mode to SD Overview 5 (S5-1 and S5-2 to ON) and inserted SD with Design on SD Slot Overview R
- Press Power Button on Enclosure or on Overview 3
- For more detailed check Reference Design description
...
Notes
Page properties |
---|
|
In this Section you must refer to the Resources Page for the particular module. For Example: TE0728 Resources |
...
Links to all documentation and download resources:
...