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- Overview of Boot Mode, Reset, Enables.
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
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anchor | Table_OV_RST |
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title | Reset process. |
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Signal | Push Button | Pin Header | Note |
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RESET | S1 | J2 | connected to nCONFIG |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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I/Os on Pin Headers and Connectors
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anchor | Table_SIP_GIOs |
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title | General I/Os to Pin Headers and connectors information |
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orientation | portrait |
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FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
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Bank 1A | J1 | 7 | 3.3V | AIN0...6 | Bank 1B | J4 | 5 | 3.3V | JTAG interface | Bank 2 | J1 | 4 | 3.3V | DIO2...5 | Bank 5 | J2 | 9 | 3.3V | DIO6...14 | J1 | 2 | 3.3V | DIO0...1 | Bank 8 | J2 | 1 | 3.3V | RESET |
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FPGA I/O Banks
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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anchor | Table_OV_BP |
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title | Boot process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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cellHighlighting | true |
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MODE Signal State | Boot Mode
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anchor | Table_OVOBP_RSTIOs |
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title | Reset process.FPGA I/O Banks |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Signal | B2B | I/O | Note |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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FPGA Bank | I/O Signal Count | Connected to | Notes |
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Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 | 1 | Jumper, J3 | AIN7 | Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | Bank 2
| 4 | 1x14 Pin header, J1 | D2...5 | 5 | A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | 1 | 12MHz Oscillator, U7 | CLK12M | 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | 2 | 1x14 Pin header, J1 | DIO0...1 | 1 | D12_R | DIO12 | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | 2 | SDRAM, U2 | DQM0...1 | 1 | D11_R | DIO11 | Bank 8
| 8 | User Red LEDs, D2...9 | LED0...7 | 6 | SPI Flash, U5 | F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn | 1 | Red LED, D10 | CONF_DONE | 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | 1 | Push Button, S2 | USER_BTN |
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JTAG Interface
JTAG access to the TExxxx TEI0015 SoM through B2B pin header connector JMXJ4.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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orientation | portrait |
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B2B Pin Header Connector | Note |
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TMS | J4-6 |
| TDI | TDOJ4-5 |
| TDO | J4-4 |
| TCK | J4-3 |
| JTAG_EN |
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On-board Peripherals
Page properties |
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| you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Page properties |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP_MIOs |
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title | MIOs pinsOn board peripherals |
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orientation | portrait |
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repeatTableHeaders | default |
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style | widths |
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MIO Pin | Connected to | B2B | Notes |
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SDRAM
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Page properties |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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Quad SPI Flash Memory
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Notes :
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Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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anchor | Table_OBP_SDRAM |
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title | SDRAM interface IOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
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Address inputs | A0 ... A13 | bank 3 | - | Bank address inputs
| BA0 / BA1 | bank 3 | - | Data input/output | DQ0 ... DQ15 | bank 6 | - | Data mask | DQM0 ... DQM1 | bank 6 | - | Clock | CLK | bank 3 |
| Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | WE | bank 3 | Write Enable |
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FTDI FT2232H
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
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anchor | Table_OBP_SPIFTDI |
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title | Quad SPI interface MIOs FTDI chip interfaces and pins |
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cellHighlighting | true |
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MIO FTDI Chip U3 Pin | Signal Schematic |
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U?? Pin |
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anchor | Table_OBP_RTC |
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title | I2C interface MIOs and pins |
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ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | ADBUS1 | TDI | FPGA bank 1B, pin F5 | ADBUS2 | TDO | FPGA bank 1B, pin F6 | ADBUS3 | TMS | FPGA bank 1B, pin G1 | BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable | BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user configurable | BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable | BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable | BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user configurable | BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
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SPI Flash Memory
On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
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anchor | Table_OBP_I2C_RTCQSPI |
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title | I2C Address for RTCQuad SPI Flash memory interface |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | I2C Address | Designator | Notes |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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Signal Schematic Name | Connected to | Notes |
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F_CS | FPGA bank 8, pin B3 | chip select | F_CLK | FPGA bank 8, pin A3 | clock | F_DI | FPGA bank 8, pin A2 | data in / out | nSTATUS | FPGA bank 8, pin C4 | data in / out, configuration dual-purpose pin of FPGA | DEVCLRN | FPGA bank 8, pin B9 | data in / out, configuration dual-purpose pin of FPGA | F_DO | FPGA bank 8, pin B2 | data in / out |
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EEPROM
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
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anchor | Table_OBP_I2C_EEPROMEEP |
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title | I2C address for EEPROM interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | I2C Address | Designator | Notes |
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LEDs
Schematic | Connected to | Notes |
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EECS | FTDI U3, Pin EECS |
| EECLK | FTDI U3, Pin EECLK |
| EEDATA | FTDI U3, Pin EEDATA |
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A2D Convertor
The TEI0010 board is equipped with the Analog Devices AD4003BCPZ, 18-bit A2D converter (ADC).
Scroll Title |
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anchor | Table_OBP_LEDA2D |
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title | On-board LEDsA2D converter interface and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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SchematicColor | Active LevelNote | |
DDR3 SDRAM
Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
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IN+ | Diff Amplifier U14, VOUT- |
| IN- | Diff Amplifier U14, VOUT+ |
| SDI | Bank 2, ADC_SDI |
| SDO | Bank 2, ADC_SDO |
| SCK | Bank 2, ADC_SCK |
| CNV | Bank 2, ADC_CNV |
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LEDs
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anchor | Table_OBP_ETHLED |
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title | Ethernet PHY to Zynq SoC connectionsOn-board LEDs |
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orientation | portrait |
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Bank | Signal Name | ETH1 | ETH2 | Signal Description |
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Designator | Color | Connected to | Active Level | Note |
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D2...9 | Red | LED1...8 | Active High | User LEDs | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | D1 | Green | 3.3V Power Rail | Active High | After power on it will be on |
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Micro-USB2 Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
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anchor | Table_OBP_CANUSB |
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title | CAN Tranciever interface MIOsMicro USB-2 connector pins |
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orientation | portrait |
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sortDirection | ASC |
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sortEnabled | false |
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cellHighlighting | true |
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BankSchematic | U?? Pin | Notes | D-Tx | Driver Input | R-Rx | Reciever OutputVBUS | USB_VBUS | It is connected to GND | D+ | FTDI U3, DP pin |
| D- | FTDI U3, DM pin |
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Clock Sources
Scroll Title |
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anchor | Table_OBP_CLK |
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title | Osillators |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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DesignatorClock Source | DescriptionSchematic Name | Frequency | Note | MHz | MHz | KHz |
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Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
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Power and Power-On Sequence
Page properties |
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power To power-up the module, power supply with minimum current capability of xx A for system startup 1A is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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orientation | portrait |
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sortDirection | ASC |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 3 |
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diagramName | TEI0015 |
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anchor | Figure |
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title | Power Distribution |
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simpleViewer | false |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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Image Added |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power-On Sequence
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 3 |
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diagramName | TEI0015_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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Scroll Only |
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Image Added | Create DrawIO object here: Attention if you copy from other page, objects are only linked. | Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
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...
Scroll Title |
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anchor | Table_PWR_PR |
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title | Module power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Connector Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Notes |
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J2
| VIN | 5V | Input |
| 3.3V | 3.3V | Output |
| 5V | 5V | Output |
| J9 | USB_VBUS | 5V | Input |
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes
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Bank Voltages
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Notes |
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Bank 1A | VCCIO1A | 3.3V |
| Bank 1B | VCCIO1B | 3.3V |
| Bank 2 | VCCIO2 | 3.3V |
| Bank 3 | VCCIO3 | 3.3V |
| Bank 5 | VCCIO5 | 3.3V |
| Bank 6 | VCCIO6 | 3.3V |
| Bank 8 | VCCIO8 | 3.3V | Notes
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Board to Board Connectors
...
Scroll Title |
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Description | Min | Max | Unit | | Min | Max | Unit | Reference Document |
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VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V |
| I/O Input voltage for FPGA I/O bank | -0.5 | 4.12 | V | Intel MAX 10 datasheet | Voltage on ADC IC U15 pins | -5.0 | 5.0 | V | AD4003BCPZ datasheet | Analog reference voltage on IC U15 | 5.0 | 5.0 | V | AD4003BCPZ datasheet | Storage Temperature | -40 | +85 | °C |
V | V | V | V | V | V | V | V
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Recommended Operating Conditions
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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ParameterUnitsV | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V |
| I/O Input voltage for FPGA I/O bank | -0.5 | 4.12 | V | Intel MAX 10 datasheet | Voltage on ADC IC U15 pins | -0.1 | 5.1 | V | AD4003BCPZ datasheet | Analog reference voltage on IC U15 | 5.0 | 5.0 | V | AD4003BCPZ datasheet | Storage Temperature | 0 | +70 | °C |
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|
Physical Dimensions
Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
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Page properties |
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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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title | Physical Dimension |
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lbox | true |
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revision | 1 |
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diagramName | TEI0015_TS_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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|
Currently Offered Variants
...