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anchor	Figure_OV_BD
title	TEBA0714 block diagram

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draw.io Diagram

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anchor	Figure_OV_MC
title	TEBA0714 main components

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draw.io Diagram

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6-pin header J26 for selecting PL-bank I/O voltage
6-pin header J27 for selecting XMOD/JTAG VCCIO
Samtec Razor Beam™ LSHM-150 B2B connector, JM1
Samtec Razor Beam™ LSHM-150 B2B connector, JM2
XMOD header, JX1
Ultra small SMT coaxial connector, J5
Ultra small SMT coaxial connector, J6
Ultra small SMT coaxial connector, J7
Ultra small SMT coaxial connector, J8
User LED D1 (green)
Voltage Regulator, U1
User Red LED D2
User Green LED D1 User LED D2 (red)
SFP+ Connector, J1
Red LED D3 (red) , indicating FPGA's 'Programming DONE'-signalSFP+ Connector, J1
10-pin header solder pads J4 for access to SoM's PL I/O-banks (LVDS pairs possible)
16-pin header solder pads J3, JTAG/UART header with ADC and MGT clock input
50-pin header solder pads J20 for access to SoM's PL I/O-banks (LVDS pairs possible)
50-pin header solder pads J17 for access to SoM's PL I/O-banks (LVDS pairs possible)

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anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

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B2B Connector	I/O Signal Count	Voltage Level	Notes
JM1	User I/O	54 single ended or 27 differential	-
MGT lanes	4 differential pairs, 2 lanes	-
MGT reference clock input	1	-
JTAG	4	-
SoM control signals	2	'PROG_B', 'DONE'
ADC interface	1 differential pair	-
JM2	User I/O	36 single ended or 18 differential	-
SFP+ Interface control signals	8	-
QSPI interface	6	-
UART interface	2	-
User LEDs	2	Red, Green
SoM control signals	1	'BOOTMODE'

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