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Scroll Title |
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anchor | Table_SIP_FMC |
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title | FMC connectors information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FMC Signal | Intel Cyclone V Direction | I/O Signal Count (Single Ended/Differential) | Voltage Level | Notes |
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LA0...1 | RX and TX | 4 / 2 | FMC_VADJ | Connected to RX and TX pins at the Intel Cyclone V |
| LA2LA3, LA5, LA7, ...15, LA17...18LA33 | RX | 32 / 16 | FMC_VADJ |
| LA16LA2, LA4, LA6, LA19 ...33, LA32 | TX | 32 / 16 | FMC_VADJ |
| CLK0...1 | RX | 4 / 2 | FMC_VADJ |
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Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA and the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
Quad SPI Flash memory U6 is connected to the HPS bank 7B and U15 to FPGA bank 3A.
Scroll Title |
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anchor | Table_OBP_QSPI_HPS |
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title | HPS Quad SPI interface signals and connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal Name | QSPI Flash Memory U6 Pin | FPGA Pin |
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QSPI_CS/BOOTSEL1 | S#, Pin C2 | Bank 7B, Pin A18 | QSPI_CLK | C, Pin B2 | Bank 7B, Pin D19 | QSPI_DATA0 | DQ0, Pin D3 | Bank 7B, Pin C20 | QSPI_DATA1 | DQ1, Pin D2 | Bank 7B, Pin H18 | QSPI_DATA2 | DQ2, Pin C4 | Bank 7B, Pin A19 | QSPI_DATA3 | DQ3, Pin D4 | Bank 7B, Pin E19 | QSPI_RST | RST#, Pin A4 | Bank 7A, Pin E24 |
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Scroll Title |
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anchor | Table_OBP_QSPI_FPGA |
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title | FPGA Quad SPI interface signals and connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal Name | QSPI Flash Memory U15 Pin | FPGA Pin |
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nCSO | S#, Pin C2 | Bank 3A, Pin AB8 | AS_DCK | C, Pin B2 | Bank 3A, Pin U7 | AS_DATA0 | DQ0, Pin D3 | Bank 3A, Pin AE6 | AS_DATA1 | DQ1, Pin D2 | Bank 3A, Pin AE5 | AS_DATA2 | DQ2, Pin C4 | Bank 3A, Pin AE8 | AS_DATA3 | DQ3, Pin D4 | Bank 3A, Pin AC7 | AS_RST | RST#, Pin A4 | Bank 7A, Pin B22 |
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Programmable Clock Generator
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U3) to generate various reference clocks for the module.
Scroll Title |
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anchor | Table_OBP_PLL |
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title | Programmable quad PLL clock generator inputs and outputs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Si5338A Pin | Signal Name / Description | Connected to | Direction | Notes |
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IN1 | - | Not Connected | Input | Not used | IN2 | - | GND | Input | Not used | IN3 | Reference input clock | U48, Pin 3 | Input | 25.000000 MHz oscillator U48, SiT8208 | IN4 | - | GND | Input | I2C slave device address LSB | IN5 | - | Not Connected | Input | Not used | IN6 | - | GND | Input | Not used | SCL | HPS_I2C_SCL | HPS I2C Bus U10, Pin H23 | Input | I²C interface muxed to FPGA Slave address: 0x70. | SDA | HPS_I2C_SDA | HPS I2C Bus U10, Pin A25 | Input / Output | I²C interface muxed to FPGA Slave address: 0x70. | CLK0A/B | CLK_B3B_p/n | U10, Pin AF14/15 | Output | Clock to FPGA bank 3B | CLK1A/B | CLK_B4A_p/n | U10, Pin AA16/AB17 | Output | Clock to FPGA bank 4A | CLK2A | CLK_50MHz_MAX10 | U41, Pin H6 | Output | Clock to Intel MAX10 bank 2 | CLK2B | HPS_CLK2_25MHz | U10, Pin F25 | Output | Clock to HPS bank 7A | CLK3A/B | CLK_B5B_p/n | U10, Pin Y26/27 | Output | Clock to HPS bank 5B |
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Oscillators
The FPGA module has following reference clocking source provided by an on-board oscillator:
Scroll Title |
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anchor | Table_OBP_OSC |
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title | Reference clock signals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Clock Source | Frequency | Signal Schematic Name | Clock Destination | Notes |
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U48, SiT8208AI
| 25.0 MHz
| CLK_25MHz_R
| Si5338A PLL U3, Pin 3 (IN3) |
| HPS_CLK1_25MHz | HPS Bank 7A U10, Pin D25 |
| ETH_XTAL_IN | ETH PHY U1, Pin 9 |
| U32, SiT8208AI | 12.0 MHz | OSCI | FT2232H U21, Pin 3 |
| U34, SiT8008BI | 24.0 MHz | USB_CLK24_HUB | USB Hub U33, Pin 33 |
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| USB_CLK24_PHY | USB PHY U8, Pin 26 |
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I2C
The TEI0022 provides two independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The other bus is used to handle the on-board I2C devices.
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Scroll Title |
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to HPS connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Bank | Signal Name | ETH | Signal Description |
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7B | ETH_TXCK |
| RGMII Transmit Reference Clock | 7B | ETH_TXD0 |
| RGMII Transmit Data 0 | 7B | ETH_TXD1 |
| RGMII Transmit Data 1 | 7B | ETH_TXD2 |
| RGMII Transmit Data 2 | 7B | ETH_TXD3 |
| RGMII Transmit Data 3 | 7B | ETH_TXCTL |
| RGMII Transmit Control | 7B | ETH_RXCK |
| RGMII Receive Reference Clock | 7B | ETH_RXD0 |
| RGMII Receive Data 0 | 7B | ETH_RXD1 |
| RGMII Receive Data 2 | 7B | ETH_RXD2 |
| RGMII Receive Data 3 | 7B | ETH_RXD3 |
| RGMII Receive Data 4 | 7B | ETH_RXCTL |
| RGMII Receive Control | 7C | ETH_RST |
| Reset | 7B | ETH_MDC |
| Management Data Clock | 7B | ETH_MDIO |
| Management Data I/O | 7B | PHY_INT |
| Interrupt |
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Oscillators
Scroll Title |
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anchor | Table_OBP_CLK |
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title | Osillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Description | Frequency | Note |
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| U37 | FPGA | 50 MHz | Bank 5B and MAX10 | U35 | FPGA | 50 MHz | Bank 4A and 3B |
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| U44 | HPS, Ethernet | 25 MHz | HPS CLK1 |
| HPS |
| HPS CLK2 | U32 | FTDI | 12 MHz |
| U34 | USB HUB, PHY | 24 MHz |
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| HPS | 25 MHz | CLK1 HPS SOCKIT |
| HPS | 25 MHz | CLK2 HPS SOCKIT |
| FPGA | 50 MHz | Bank 3B SOCKIT |
| FPGA | 50 MHz | Bank 4A SOCKIT |
| FPGA | 50 MHz | Bank 5B SOCKIT |
| FPGA | 50 MHz | Bank 8A SOCKIT |
| FPGA | 50 MHz | Pin P8/9 SOCKIT |
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