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Scroll Title |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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|
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
Storage device name | Content | Notes |
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SPI Flash | Not programmed |
| EEPROM | Not Programmed |
| Clock Generator | Programmed |
|
|
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Scroll Title |
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anchor | Table_OV_RST |
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title | Reset Process. |
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|
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Signal | Description | Note |
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PRSNT_TOP | Lattice MachXO Configuration Pin |
| PROG_B | Artix 7 Configuration Pin | Connected Pulled up to 1.8 |
|
Signals, Interfaces and Pins
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Scroll Title |
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anchor | Table_SIP_Coaxial |
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title | Coaxial Connectors information |
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|
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Designator | Schematic | Connected to | Notes |
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J2 | GA_OUT | Serializer, U5 | Output Serializer |
| J3 | GB_OUT | Serializer, U6 | Output Serializer |
| J4 | GC_OUT | Serializer, U7Output Serializer |
| J5 | GD_OUT | Serializer, U8Output Serializer |
|
|
JTAG Interface
The Lattice MachXO (U15) is available to meet the requirement of a CPLD, JTAG access to the MachXO is available through FMC Adapter J6. JTAG access to the Artix 7(U1) is available via MachXO, Bank 2.
Scroll Title |
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anchor | Table_SIP_CPLDJTG |
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title | CPLD JTAG pins connection |
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|
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
JTAG Signal | B2B Connector | Notes |
---|
FMC_TMS | J6F-TCK |
| FMC_TDI_TOP | J6F-J1-TDI |
| FMC_TDO_TOP | J6F-TDO |
| FMC_TCK | J6F-TCK |
| JTAGEN | Pulled down |
|
|
Scroll Title |
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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|
Scroll Table Layout |
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orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
JTAG Signal | Connected to | Note |
---|
TMS | Lattice MachXO, U15 BankArtix 7 FPGA, U1 | Bank 2 Bank 0 | TDI | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | TDO | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | TCK | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | INIT | Artix 7 FPGA, U1 | Connected Pulled up to 1.8 |
|
On-board Peripherals
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