Page History
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Template Revision 1.9 - on construction Design Name always "TE Series Name" + optional CPLD Name + "CPLD" |
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
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Table of contents
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- JTAG routing
- Boot Mode settings
- LEDPower
Firmware Revision and supported PCB Revision
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Name / opt. VHD Name | Direction | Pin | Bank Power | Description | Note:||||
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C_TCK | in | 30 | 3.3VIN | JTAG B2B | ||||
C_TDI | in | 32 | 3.3VIN | JTAG B2B | ||||
C_TDO | out | 1 | 3.3VIN | JTAG B2B | ||||
C_TMS | in | 29 | 3.3VIN | JTAG B2BEN1 | ||||
PG_FPD | in | 27 | 3.3VIN | Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedbackGOOD from SOC FPD regulators | ||||
RESIN | inout | User_LED | out | 4 | 3.3VIN | user defined or status, see LED description | 1.8V input ERR_OUT(PS_ERROR_OUT) | Reset control and minitoring |
EN_MGT | outN.C. | 5 | 3.3VIN | / currently_not_used | 1.8V input ERR_STATUS as inputenable GTR Power Domain | |||
JTAGEN | in | 26 | 3.3VIN | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) | ||||
MODE | in | 25 | 3.3VIN | Boot Mode for Zynq/ZynqMP Devices (Flash or SD) | ||||
MODE0 | out | 12 | 1.8V | ZynqMP Boot Mode Pin 0 | ||||
MODE1 | out | 13 | 1.8V | ZynqMP Boot Mode Pin 1 | ||||
MODE2 | out | 14 | 1.8V | ZynqMP Boot Mode Pin 2 | ||||
MODE3 | out | 16 | 1.8V | ZynqMP Boot Mode Pin 3 | ||||
NOSEQ | inout | 23 | 3.3VIN | usage CPLD Variant depends | ||||
PGOOD | outinout | 28 | 3.3VIN | Module Power Good (only Feedback from EN1).FPD + MGT(if not disabled by user)) | ||||
PG_MGTPHY_LED1 | in | 17 | 1.8V | ETH PHY LED1 / currently_not_usedPower Good of GTR power domain | ||||
TCK | out | 9 | 1.8V | JTAG ZynqMP | ||||
TDI | out | 8 | 1.8V | JTAG ZynqMP | ||||
TDO | in | 10 | 1.8V | JTAG ZynqMP | ||||
TMS | out | 11 | 1.8V | JTAG ZynqMP | ||||
X0 | in | 20 | VCCO_65 | FPGA IO (FPGA Pin H1) / Enable User LED (negative) | output Firmware variantX0 X1 can be used to disable MGT Power | |||
X1 | in | 21 | VCCO_65 | FPGA IO (FPGA Pin J1)/ Connect to User LED | output PHY_LED1X0 X1 can be used to disable MGT Power |
Functional Description
JTAG
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NOSEQ*: Please check the carrier board documentation, before using the SD/QSPI/JTAG firmware variant on TE0820. In the most cases special carrier CPLD firmware is needed. |
Power
PGOOD is EN1. There is no additional power management controlled by CPLD.
LED
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*It's recommended to forward this signal to a carrier LED if status check is needed.
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is zero if PG_FPD is low or if PG_MGT is low (as long as it is enabled by user) otherwise it's high impedance
Appx. A: Change History
For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD
Revision Changes
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X1 is input for USER LED
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blink modes for QSPI/SD firmware
- REV02 to REV03
- new Boot Mode variants
- new X0 status blink sequencing
- REV01 to REV02
- initial release
- Boot Mode variants
- X1
- Remove ERR_STATUS
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV04 | REV03 |
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v.1 | REV04 | REV03 | John Hartfiel |
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v.1 | REV04 | REV03 | Page info | | created-user | created
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- Initial release
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