| Date | Vivado | Project Built | Authors | Description |
|---|
| 2020-03-25 | 2019.2 | TEB0911-test_board_noprebuilt-vivado_2019.2-build_8_20200325084706.zip
TEB0911-test_board-vivado_2019.2-build_8_20200325084633.zip | John Hartfiel | |
| 2020-02-24 | 2019.2 | TEB0911-test_board_noprebuilt-vivado_2019.2-build_6_20200224080741.zip
TEB0911-test_board-vivado_2019.2-build_6_20200224080728.zip | John Hartfiel | - bugfix PL Design (all MGT buffer enabled)
|
| 2020-02-13 | 2019.2 | TEB0911-test_board_noprebuilt-vivado_2019.2-build_5_20200213114513.zip
TEB0911-test_board-vivado_2019.2-build_5_20200213112730.zip | John Hartfiel | - 2019.2 update
- new assembly variants
- Vitis support
- FSBL SI programming procedure update
- petalinux device tree and u-boot update
- reduced DDR speed (see Xilinx Datasheet)
|
| 2018-11-26 | 2018.2 | TEB0911-test_board_noprebuilt-vivado_2018.2-build_03_20181126132622.zip
TEB0911-test_board-vivado_2018.2-build_03_20181126132607.zip | John Hartfiel | - new assembly variant
- add init.sh
|
| 2018-07-20 | 2018.2 | TEB0911-test_board_noprebuilt-vivado_2018.2-build_02_20180719153443.zip
TEB0911-test_board-vivado_2018.2-build_02_20180719153429.zip | John Hartfiel | |