Page History
...
Page properties | ||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||
Important General Note:
|
Scroll pdf ignore | ||||
---|---|---|---|---|
Table of contents
|
Overview
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.
Key Features
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
Excerpt |
---|
|
Revision History
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
Scroll Title | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Release Notes and Know Issues
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
anchor | Table_KI |
---|---|
title | Known Issues |
...
Do not use HW Manager connection, or if debugging is nessecary:
- Boot linux with usb terminal
- From the terminal: root root mount ifconfig eth0
- Open two new SSH terminals via ethernet: root root , run user application ...
- Exit and close the usb terminal
...
|
Release Notes and Know Issues
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Scroll Title | ||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||
|
Requirements
Software
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Scroll Title | ||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||
|
Hardware
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.
Design supports following carriers:
Scroll Title | ||||
---|---|---|---|---|
|
Requirements
Software
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
anchor | Table_SW |
---|---|
title | Software |
...
Hardware
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.
Design supports following carriers:
|
Additional HW Requirements:
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||
|
Content
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
Scroll Title | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
|
Additional Sources
Scroll Title | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||
Scroll Title | |||||||||||||||||||||||
| |||||||||||||||||||||||
|
...
|
Prebuilt
Page properties | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
Notes :
| AHW
| Additional Hardware
| ||||||||||||||||||||||||||||
Additional Hardware | Notes | |||||||||||||||||||||||||||||
DP Monitor | Optional HW | |||||||||||||||||||||||||||||
USB Keyboard | Optional HW Can be used to get access to console which is show on DP | |||||||||||||||||||||||||||||
USB Stick | Optional HW USB was tested with USB memory stick | |||||||||||||||||||||||||||||
Sata Disk | Optional HW | |||||||||||||||||||||||||||||
PCIe Card | Optional HW | |||||||||||||||||||||||||||||
ETH cable | Optional HW Ethernet works with DHCP, but can be setup also manually | |||||||||||||||||||||||||||||
SD card | with fat32 partiton |
Content
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
|
Scroll Title | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||
Scroll Title | ||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||
|
Additional Sources
...
anchor | Table_ADS |
---|---|
title | Additional design sources |
...
|
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Prebuilt
Page properties | |||||
---|---|---|---|---|---|
| |||||
Scroll Title | |||||
| |||||
Scroll Table Layout | |||||
orientation | portrait | ||||
sortDirection | ASC | ||||
repeatTableHeaders | default | style | widths | ||
sortByColumn | 1 | ||||
sortEnabled | false | ||||
cellHighlighting | true | ||||
File | File-Extension | Description | |||
BIF-File | *.bif | File with description to generate Bin-File | |||
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | |||
BIT-File | *.bit | FPGA (PL Part) Configuration File | |||
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | |||
Debian SD-Image | *.img | Debian Image for SD-Card | |||
Diverse Reports | --- | Report files in different formats | |||
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | |||
LabTools Project-File | *.lpr | Vivado Labtools Project File | |||
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | |||
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | |||
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | |||
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | |||
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems | |||
Scroll Title | |||||
| |||||
Scroll Table Layout | |||||
orientation | portrait | ||||
sortDirection | ASC | ||||
repeatTableHeaders | default | style | widths | ||
sortByColumn | 1 | ||||
sortEnabled | false | ||||
cellHighlighting | true | ||||
File | File-Extension | Description | |||
BIF-File | *.bif | File with description to generate Bin-File | |||
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | |||
BIT-File | *.bit | FPGA (PL Part) Configuration File | |||
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | |||
Diverse Reports | --- | Report files in different formats | |||
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | |||
LabTools Project-File | *.lpr | Vivado Labtools Project File | |||
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | |||
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Page properties | ||||
---|---|---|---|---|
| ||||
|
Reference Design is available on:
Design Flow
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which ends with *_tebf0808
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
...
|
Reference Design is available on:
Design Flow
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which ends with *_tebf0808
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Launch
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For basic board setup, LEDs... see: TEBF0808 Getting Started
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Not used in this example.
SD
- Format the SD Card with SD Card Formatter or other tool
- Write the Debian image or Ubuntu image file on SD Card with Win32DiskImager
- It will automatically in BOOT directory two DTB file generated
- system_sd.dtb : This file ist used , if the root file system is located on SD card.
- system_harddisk.dtb : This file ist used , if the root file system is located on hard disk.
- Note: To use one of the DTB files, this file must be renamed to system.dtb
- Rename the system_sd.dtb file in BOOT directory to system.dtb
- Copy Petalinux Image (not use image.ub), system.dtb and Boot.bin files on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 70156402
- Connect UART USB (JTAG XMOD)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect Sata Disc
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional) Connect Network Cable
- Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- Debian Desktop
- Use connected mouse + keyboard for interaction with GUI
- Start the GUI with the command : startx
- Web Browser Dillo open console and type dillo or use browser
- open console and start video or audio with "mplayer <video or audio file>"
- Ubuntu Desktop
- Use connected mouse + keyboard for interaction with GUI
- Start the GUI with the command : startx
- Web Browser Mozilla firefox can be used.
- Audio or Vider file can also be performed directly in GUI
Hard Disk (optional)
To locate root file system on Hard disk:
- Plug in SD Card that you have prepared mit root file system
- Plug in Hard Disk in Sata port on the carrier board
- Format the hard disk by the following command:
- mkfs.ext4 /dev/sda
- Edit the fstab file in directory /etc/ to mount hard disk by the following commands:
- mkdir /media/harddisk
- nano /etc/fstab
- Add this line to the fstab file and save it : /dev/sda /media/harddisk/ defaults 0 3
- Reboot
- Copy entire root file system in direcroty ROOTFS from SD card to hard disk by the following commands:
- cd /media/ROOTFS
- cp -r ./ /media/harddisk
- Edit the fstab file in directory /media/harddisk/etc/ by the following commands and save it:
- nano /media/harddisk/etc/fstab
- Edit this line to the fstab file : /dev/sda /media/harddisk/ defaults 0 1
- Comment this line: #/dev/mmcblk1p2 /media/ROOTFS defaults 0 1
- Shutdown the system
- Format the SD card
- Rename the Device Tree Blob file system_harddisk.dtb to system.dtb
- Copy the following files to SD Card:
- Image
- BOOT.bin
- system.dtb
- Plug in the SD Card and turn on the system
Vivado Hardware Manager
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For basic board setup, LEDs... see: TEBF0808 Getting Started
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible - Copy image.ub on SD-Card
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to QSPI-Boot and insered SD.
- Depends on Carrier, see carrier TRM.
- TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area
SD
- Copy image.ub and Boot.bin on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 70156402
- Connect UART USB (JTAG XMOD)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect Sata Disc
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional) Connect Network Cable
- Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB device
- PCIe type "lspci"
- Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
- Webserver to get access to Zynq
Vivado Hardware Manager
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Buttons, LEDs, Status...
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Set Enable to send Write date over RGPIO interface.
...
|
System Design - Vivado
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Block Design
Scroll Title | ||||
---|---|---|---|---|
| ||||
PS Interfaces
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Activated interfaces:
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Constrains
Basic module constrains
Code Block | ||||
---|---|---|---|---|
| ||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Code Block | ||||
---|---|---|---|---|
| ||||
#System Controller IP
#J3:31 LED_HD
set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
#J3:41
set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
#J3:45
set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
#J3:47
set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
#J3:32
set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
#J3:34
set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
#J3:36
set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
#J3:38
set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
#J3:40
set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
#J3:42
set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
#J3:46 CAN S
set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
#J3:48 LED_XMOD
set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
#J3:50 CAN TX
set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
#J3:52 CAN RX
set_property PACKAGE_PIN C14 [get_ports BASE_sc19]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
# PLL
#J4:74
#set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
# Audio Codec
#LRCLK J3:49 B47_L9_N
#BCLK J3:51 B47_L9_P
#DAC_SDATA J3:53 B47_L7_N
#ADC_SDATA J3:55 B47_L7_P
set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ]
set_property PACKAGE_PIN H14 [get_ports I2S_bclk ]
set_property PACKAGE_PIN C13 [get_ports I2S_sdin ]
set_property PACKAGE_PIN D14 [get_ports I2S_sdout |
...
anchor | Figure_VHM |
---|---|
title | Vivado Hardware Manager |
...
...
System Design - Vivado
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Block Design
Scroll Title | ||||
---|---|---|---|---|
| ||||
PS Interfaces
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Activated interfaces:
...
anchor | Table_PSI |
---|---|
title | PS Interfaces |
...
Constrains
Basic module constrains
Code Block | ||||
---|---|---|---|---|
| ||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Code Block | ||||
---|---|---|---|---|
| ||||
#System Controller IP #J3:31 LED_HD set_property PACKAGE_PIN K11 [get_ports BASE_sc0] #J3:41 set_property PACKAGE_PIN E14 [get_ports BASE_sc5] #J3:45 set_property PACKAGE_PIN C12 [get_ports BASE_sc6] #J3:47 set_property PACKAGE_PIN D12 [get_ports BASE_sc7] #J3:32 set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io] #J3:34 set_property PACKAGE_PIN K13 [get_ports BASE_sc11] #J3:36 set_property PACKAGE_PIN A13 [get_ports BASE_sc12] #J3:38 set_property PACKAGE_PIN A14 [get_ports BASE_sc13] #J3:40 set_property PACKAGE_PIN E12 [get_ports BASE_sc14] #J3:42 set_property PACKAGE_PIN F12 [get_ports BASE_sc15] #J3:46 CAN S set_property PACKAGE_PIN A12 [get_ports BASE_sc16] #J3:48 LED_XMOD set_property PACKAGE_PIN B12 [get_ports BASE_sc17] #J3:50 CAN TX set_property PACKAGE_PIN B14 [get_ports BASE_sc18] #J3:52 CAN RX set_property PACKAGE_PIN C14 [get_ports BASE_sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASEI2S_sc5lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports BASEI2S_sc6bclk ] set_property IOSTANDARD LVCMOS18 [get_ports BASEI2S_sc7sdin ] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # PLL #J4:74 #set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}] # Audio Codec #LRCLK J3:49 B47_L9_N #BCLK J3:51 B47_L9_P #DAC_SDATA J3:53 B47_L7_N #ADC_SDATA J3:55 B47_L7_P set_property PACKAGE_PIN G14 [get_ports LRCLK ] set_property PACKAGE_PIN H14 [get_ports BCLK ] set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ] set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ] set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ] set_property IOSTANDARD LVCMOS18 [get_ports BCLK ] set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ] set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ] |
Software Design - Vitis
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For SDK project creation, follow instructions from:
Application
I2S_sdout ]
|
Software Design - Vitis
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For SDK project creation, follow instructions from:
Application
Page properties | ||||
---|---|---|---|---|
| ||||
Page properties | ||||
| ||||
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. | ||||
---------------------------------------------------------- FPGA General Example: scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderhello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
SDK template in ./sw_lib/sw_apps/ available.
zynqmp_fsbl
TE modified 2019.2
...
Bootloader to load app or second bootloader from flash into DDR
FSBL
General
...
:
- Modified Files:
...
- xfsbl_main.c, xfsbl_hooks.h
...
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
- /.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5345 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
zynqmp_fsbl_flash
...
TE modified 2019.2
...
- Changed default Flash type to 5.
----------------------------------------------------------
Zynq Example:
zynq_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example:
----------------------------------------------------------
zynqmp_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
----------------------------------------------------------
General Example:
hello_te0820
Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Select Image Packaging Configuration ==> Root filesystem type ==> Select SD Card
Changes:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
# CONFIG_SUBSYSTEM_BOOTARGS_AUTO is not set
CONFIG_SUBSYSTEM_USER_CMDLINE="console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M"
CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="Image"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS
SDK template in ./sw_lib/sw_apps/ available.
zynqmp_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5345 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
zynqmp_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Activate:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
U-Boot
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
Change platform-top.h:
...
language | js |
---|
Device Tree
Code Block | ||
---|---|---|
| ||
/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; bootargs= }; }; /* "console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M"; /* notes: root=/dev/mmcblk1p2 for SD and root=/dev/sda for hard disk will be changed automatically by executing the debian/ubuntu script*/ }; }; /* notes: serdes: // PHY TYP see: dt-bindings/phy/phy.h */ /* default */ /* SD */ &sdhci1 { // disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; phys = <&lane1 4 0 2 100000000>; maximum-speed = "super-speed"; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* I2C */ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // SFP TEBF0808 PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // SFP1 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 {// SFP2 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // TEBF0808 EEPROM #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; i2c@6 { // TEBF0808 FMC #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // TEBF0808 Firefly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // TEBF0808 Firefly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { //Module PLL Si5338 or SI5345 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { //TEBF0808 CPLD #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { //TEBF0808 Firefly PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 PMOD P3 #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; |
Kernel
Start with petalinux-config -c kernel
Changes:
CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
- CONFIG_EDAC_CORTEX_ARM64=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
Applications
See: \os\petalinux\project-spec\meta-user\recipes-apps\
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
Additional Software
Page properties | ||||
---|---|---|---|---|
| ||||
Note: |
SI5345
File location <design name>/misc/Si5345/Si5345-*.slabtimeproj
General documentation how you work with these project will be available on Si5345
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties | ||||
---|---|---|---|---|
| ||||
|
i2c@7 { // TEBF0808 PMOD P3
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
}; |
Kernel
Start with petalinux-config -c kernel
Changes:
CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
- CONFIG_EDAC_CORTEX_ARM64=y
Rootfs
Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
Applications
Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
Additional Software
Page properties | ||||
---|---|---|---|---|
| ||||
Note: |
No additional software is needed.
SI5345
File location <design name>/misc/Si5345/Si5345-*.slabtimeproj
General documentation how you work with these project will be available on Si5345
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties | ||||
---|---|---|---|---|
| ||||
|
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Scroll Table Layout | | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
orientation | portrait | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
sortDirection | ASC | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
repeatTableHeaders | default | style | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
widths | 2*,*,3*,4* | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
sortByColumn | 1 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
sortEnabled | false | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
cellHighlighting | true |
Date | Document Revision | Authors | Description | |||
---|---|---|---|---|---|---|
Page info | modified-date | modified-date | ||||
dateFormat | yyyy-MM-dd |
| ||||
Page info | modified-user | modified-user |
| |||
2020-02-25 | v.19 | John Hartfiel |
| |||
2020-02-19 | v.18 | John Hartfiel |
| |||
2020-01-27 | v.17 | John Hartfiel |
| |||
2019-05-22 | v.16 | John Hartfiel |
| |||
2019-09-04 | v.13 | John Hartfiel |
| |||
2018-07-20 | v.12 | John Hartfiel |
| |||
2018-04-30 | v.10 | John Hartfiel |
| |||
2018-02-08 | v.9 | John Hartfiel |
| |||
2018-01-29 | v.4 | John Hartfiel |
| |||
2018-01-18 | v.3 | John Hartfiel |
| |||
All | ||||||
Page info | modified-users | modified-users
Legal Notices
Include Page | ||||
---|---|---|---|---|
|
...