Page History
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The Xilinx Zynq-7000 SoC used on the TE0782 module has 16 MGT transceiver lanes. All of them are wired directly to B2B connectors J1 and J3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane with data transmission rates up to 12.5Gb/s per lane (Xilinx GTX transceiver). Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Board to
| Bank | Type | Lane | Signal Name | B2B Pin | FPGA Pin |
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| 109 | GTX | 0 |
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| 110 | GTX | 0 |
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| 111 | GTX | 0 |
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| 112 | GTX | 0 |
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Board to Board Connectors
The TE0782 SoM has three 160-pin double-row ASP-122952-01 Samtec connectors on the bottom side which mate with ASP-122953-01 Samtec connectors on the baseboard. Mating height is 5 mm.Include Page 8.5 x 8.5 SoM QSH and QTH B2B Connectors 8.5 x 8.5 SoM QSH and QTH B2B Connectors
Variants Currently In Production
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| Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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| 2018-07-20 | v.33 | John Hartfiel |
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2018-07-19 | v.32 | Ali Naseri |
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| 2018-05-15 | v.22 | Ali Naseri |
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| 2018-01-31 | Ali Naseri |
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| 2017-06-07 | Jan Kumann |
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| 2017-05-23 | v.13 | Jan Kumann |
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| 2017-01-24 | v.12 | Ali Naseri |
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| 2016-06-27 | v.10 | Ali Naseri, Jan Kumann |
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Overview
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