Connected to GbE MagJack J2 LED0 (green). Also connected to J5-24 (PHY_LED0_CON).
PHY_LED1
-
Connected to GbE MagJack J2 LED1 (green). Also connected to J5-23 (PHY_LED1_CON).
PHY_INT
JB3-33
-
CONFIG
JB3-60
-
CLK125
JB3-32
PHY Clock (125 MHz) output.
ETH-RST
JB3-53
-
RGMII
JB3-31 JB3-37 - JB-44, JB3-47, JB3-57 - JB-59
Reduced Gigabit Media Independent Interface.
12 pins
12 pins.
Note
ETH-RXCK is connected via 0Ohm to JB3-31 (R18)and JB3-58 (R19). Usage depends on Module and Xilinx IP restrictions In case of performance problems remove 0Ohm resistor from the unused Pin.