| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA Bank | Schematic | Voltage | Note |
|---|
| Bank 24 HD | VCCO_HD24_44 | Variable | Max voltage 3.3V | | Bank 25 HD | VCCO_HD25_26 | Variable | Max voltage 3.3V | | Bank 26 HD | VCCO_HD25_26 | Variable | Max voltage 3.3V | | Bank 44 HD | VCCO_HD24_44 | Variable | Max voltage 3.3V | | Bank 64 HP | VCCO_64 | N.C | Not Connected | | Bank 65 HP | VCCO_65 | Variable | Max voltage 1.8V | | Bank 66 HP | VCCO_66 | 1.8V |
| | Bank 500 PSMIO | VCCO_PSIO0_500 | 1.8V |
| Bank 501 PSMIO | VCCO_PSIO1_501 | 3.3V |
| | Bank 502 PSMIO | VCCO_PSIO2_502 | 1.8V |
| | Bank 503 PSCONFIG | VCCO_PSIO3_503 | 1.8V |
| | Bank 504 PSDDR | DDR_1V2 | 1.2V |
|
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