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MicroBlaze Design with HyperRAM memory test example.
This reference designs design is bundled with a FREE evaluation edition of the commercially proven, low-cost, low-circuit area commercially proven, high performance , HyperBus Memory Controller (HBMC) memory controller IP supplied by by Synaptic Laboratories Ltd. Synaptic Labs HBMC IP is commercially proven in both Intel and Xilinx projects, and was selected by Intel. This FREE HBMC IP (SLL). This free IP evaluation license never expires, and no customer registration or NIC ID is required. You can check for and obtain Click here to find the latest version of the FREE evaluation HBMC IP from S/Labs website for Xilinx on S/Labs HBMC IP (Free Trail IP) . Please send your HBMC IP support questions to free trials of SLL’s memory controller IP for HyperBus, OctaBus, Xccela Bus, JEDEC xSPI Profile 1.0 and JEDEC xSPI Profile 2.0 for Intel, Microchip, and Xilinx FPGA. SLL IP is also qualified for use with Trenz HS CRUVI enabled boards. Please send all sales enquiry and technical support questions for SLL’s IP to info@synaptic-labs.com
Refer to http://trenz.org/te0725-info for the current online version of this manual and other available documentation.
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