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Template Revision 21.8 0 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 TEI0006 Test Board"


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DateQuartusProject BuiltAuthorsDescription
2020-0710-071919.1 Lite

TEI0001-test_board_noprebuilt-quartus_19.1.0-2020070715303320201019101714.zip

TEI0001-test_board-quartus_19.1.0-2020070715320520201019101651.zip

Thomas Dück
  • bugfixesscript update
2020-0507-120719.1 Lite

TEI0001-test_board_noprebuilt-quartus_19.1.0-2020051209585220200707153033.zip

TEI0001-test_board-quartus_19.1.0-2020051210003720200707153205.zip

Thomas Dück
  • 19.1 bugfixes
  • script update
20192020-1105-11121819.1 Lite

TEI0001-test_board_noprebuilt-quartus_1819.1.0-2019111110420120200512095852.zip

TEI0001-test_board-quartus_1819.1.0-2019111110434820200512100037.zip

Thomas Dück
  • add 19.1 update
2019-11-1118.1

TEI0001-test_board_noprebuilt-quartus_18.1-20191111104201.zip

TEI0001-test_board-quartus_18.1-20191111104348.zip

Thomas Dück
  • add bash files for Linux OS
2019-10-2818.1

TEI0001-test_board_noprebuilt-quartus_18.1-20191028120819.zip

TEI0001-test_board-quartus_18.1-20191028120521.zip

Thomas Dück
  • create project with TE scripts
  • new assembly variants
2019-04-0218.1TEI0001-03-08-C8-test_board-quartus_18.1-20190402.zipThomas Dück
  • initial release


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  • prebuilt files
  • Template Table:

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      BIN-

      File

      File-Extension

      Description

      BIF-SOPC Information File*.bifsopcinfoFile with description to generate Bin-Fileof the .qsys file to create software for the target hardware
      SRAM Object File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-sofRam configuration file
      Programmer Object File*.bitpofFPGA (PL Part) Configuration FileDebugProbes-Fileconfiguration file
      JTAG indirect configuration file*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      jicFlash configuration file
      Diverse Reports---Report files in different formats
      HardwareSoftware-PlatformApplication-Specification-FilesFile*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-elfSoftware application for NIOS II processor system




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File

File-Extension

Description

SOPC Information File*.sopcinfoFile with description of the *.qsys file to create software for the target hardware
Programmer Object File*.pofFPGA configuration file
Diverse Reports---Report files in different formats
Software Application File*.elfSoftware
Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

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File

File-Extension

Description

SOPC Information File*.sopcinfoFile with description of the *.qsys file to create software for the target hardware
Programmer Object File*.pofFPGA configuration file
Diverse Reports---Report files in different formats
Software Application File*.elfSoftware application for NIOS II processor system

Download

Reference design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.

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Important set new Quartus version
application for NIOS II processor system


Download

Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.

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Reference Design is available on:

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Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.

See also:

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true
idComments
Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.

See also:


The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.

TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality

  1. Open create_project_win.cmd/create_project_linux.sh:
    'Create Project' GUI exampleImage Added
  2. Select Board in "

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  1. Board selection"
  2. Click on "Create project" button to create project
    1. (optional for manual changes) Select correct quartus installation path in "<design_name>/settings/design_basic_settings.tcl"

Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

MAX10 Flash

  1. Connect the Module to USB-Port
  2. Open create_project_win.cmd/create_project_linux.sh
  3. Select correct board in "Board selection"
  4. Click on "Program device" button
    1. if prebuilt files are available:

    'Create Project' GUI exampleImage RemovedSelect Board in "Board selection"
    1. select "Program prebuilt file"
    2. using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
    3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
  5. Click on "Create project" button to create project
    1. (optional for manual changes) Select correct quartus installation path in "<design_name>/settings/design_basic_settings.tcl"

Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

MAX10 Flash

  1. Connect the Module to USB-Port
  2. Open create_project_win.cmd/create_project_linux.sh
  3. Select correct board in "Board selection"
  4. Click on "Program device" button
    1. if prebuilt files are available: select "Program prebuilt file"
    2. using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
    3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
  5. Click on "Start program device" button

JTAG

Not used on this example.

Usage

  1. Prepare Hardware like described on section 74976247
  2. Connect UART USB (most cases same as JTAG)

UART

  1. Open Serial Console (e.g. PuTTY)
    1. COM Port: Win OS see device manager, Linux OS see  dmesg | grep tty  (UART is *USB1)
    2. Speed: 115200
  2. Press reset button on the module
  3. Toggle between following modes by pressing user button
    1. Spirit level
    2. Winbond SPI flash memory test
    3. Shift register sequence
    4. Knightrider sequence
    5. Case statement sequence

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  1. Start program device" button

JTAG

Not used on this example.

Usage

  1. Prepare Hardware like described on section 74976247
  2. Connect UART USB (most cases same as JTAG)

UART

  1. Open Serial Console (e.g. PuTTY)
    1. COM Port: Win OS see device manager, Linux OS see  dmesg | grep tty  (UART is *USB1)
    2. Speed: 115200
  2. Press reset button on the module
  3. Toggle between following modes by pressing user button
    1. Spirit level
    2. Winbond SPI flash memory test
    3. Shift register sequence
    4. Knightrider sequence
    5. Case statement sequence

System Design - Quartus

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  • Description of Block Design - Project, Block Design - Platform Desginer, ... Block Design Pictures from Export...

Block Design

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Software Design - SDK

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Note:
  • optional chapter separate

  • sections for different apps

Application

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  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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Software Design - SDK

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  • sections for different apps

Application

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----------------------------------------------------------

General Example:

hello_tei0006

Hello TEI0006 is a Quartus Hello World example as endless loop instead of one console output.


Template location: <design_name>/source_files/software/

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