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Additional Sources

Additional HW Requirements:

Prebuilt

Content

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional Sources

Prebuilt

• • -alignment center title Prebuilt files

    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Source *.scr Distro Boot file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Hardware-Platform-

• • Description-

• • File *.xsa Exported Vivado

• • hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0727 "Zynqberry Demo1" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
   
   1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported XSA
   
   1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
      2. For 128MB and 64MB only:Netboot Offset must be reduced manually, see 69107715
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\<DDR size>" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<DDR size>", if exist, otherwise "prebuilt\os\petalinux\<short name>"
8. Generate Programming Files with Vitis
   
   1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0727 "Zynqberry Demo1" Reference Design

Design Flow

See also:

• Xilinx Development Tools

• Vivado Projects - TE Reference Design

•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell

2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection
   3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

1. Connect JTAG and power on the carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
            optional "TE::pr_program_flash -swapp hello_te0726" possible
4. Copy image.ub on SD-Card
   • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
   • Important: Do not copy Boot.bin on SD(is not used see SD note), only other files.
5. Copy init.sh on SD-Card
   • location: <design_name>/misc/sd/
6. Insert SD-Card

SD

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (u-boot)

JTAG

Not used on this Example.

Usage

1. Prepare HW like described in section 69107715
2. Connect UART USB (most cases same as JTAG)
3. Insert SD Card with image.ub
4. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads U-boot from QSPI into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
      Note: Wait until Linux boot finished For Linux Login use:
      
      1. User Name: root
      2. Password: root
3. You can use a Linux shell now.
   1. I2C 1 Bus type: i2cdetect -y -r 5
      Bus 0...5 possible
   2. USB: insert USB device
4. Camera stream will be enabled via init.sh script on SD
5. Take image from camera (must be enabled with init.sh scripts):
   1. write image to webserver: fbgrab -d /dev/fb1 /srv/www/camera.png
   2. Display image on host PC: http://<ZynqBerry IP>/camera.png

System Design - Vivado

Block Design

PS Interfaces

Activated interfaces:

Constraints

Basic module constraints

#
# Common BITGEN related settings for TE0727 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Design specific constraint

#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

set_property PACKAGE_PIN G11 [get_ports {CEC_A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CEC_A[0]}]
set_property PACKAGE_PIN H13 [get_ports {HPD_A}]
set_property IOSTANDARD LVCMOS33 [get_ports {HPD_A}]
set_property PACKAGE_PIN G14 [get_ports {GLED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GLED[0]}]
set_property PACKAGE_PIN G12 [get_ports {IIC_A_scl_io}]
set_property PACKAGE_PIN H12 [get_ports {IIC_A_sda_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {IIC_A_*}]
set_property PACKAGE_PIN K12 [get_ports {CT_HPD[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CT_HPD[0]}]

set_property PACKAGE_PIN F12 [get_ports {HDMI_TXC_P}]
set_property PACKAGE_PIN E13 [get_ports {HDMI_TXC_N}]
set_property PACKAGE_PIN E11 [get_ports {HDMI_TX_P[0]}]
set_property PACKAGE_PIN E12 [get_ports {HDMI_TX_N[0]}]
set_property PACKAGE_PIN G15 [get_ports {HDMI_TX_P[1]}]
set_property PACKAGE_PIN F15 [get_ports {HDMI_TX_N[1]}]
set_property PACKAGE_PIN F14 [get_ports {HDMI_TX_N[2]}]
set_property PACKAGE_PIN F13 [get_ports {HDMI_TX_P[2]}]
set_property IOSTANDARD TMDS_33 [get_ports {HDMI_*}]

set_property PACKAGE_PIN J11 [get_ports {GPIO_tri_io[0]}]
set_property PACKAGE_PIN H11 [get_ports {GPIO_tri_io[1]}]
set_property PACKAGE_PIN J15 [get_ports {GPIO_tri_io[2]}]
set_property PACKAGE_PIN L15 [get_ports {GPIO_tri_io[3]}]
set_property PACKAGE_PIN N13 [get_ports {GPIO_tri_io[4]}]
set_property PACKAGE_PIN P8  [get_ports {GPIO_tri_io[5]}]
set_property PACKAGE_PIN M10 [get_ports {GPIO_tri_io[6]}]
set_property PACKAGE_PIN L12 [get_ports {GPIO_tri_io[7]}]
set_property PACKAGE_PIN M11 [get_ports {GPIO_tri_io[8]}]
set_property PACKAGE_PIN P10 [get_ports {GPIO_tri_io[9]}]
set_property PACKAGE_PIN P9  [get_ports {GPIO_tri_io[10]}]
set_property PACKAGE_PIN K15 [get_ports {GPIO_tri_io[11]}]
set_property PACKAGE_PIN M9  [get_ports {GPIO_tri_io[12]}]
set_property PACKAGE_PIN L13 [get_ports {GPIO_tri_io[13]}]
set_property PACKAGE_PIN L14 [get_ports {GPIO_tri_io[14]}]
set_property PACKAGE_PIN M15 [get_ports {GPIO_tri_io[15]}]
set_property PACKAGE_PIN J14 [get_ports {GPIO_tri_io[16]}]
set_property PACKAGE_PIN N14 [get_ports {GPIO_tri_io[17]}]
set_property PACKAGE_PIN K11 [get_ports {GPIO_tri_io[18]}]
set_property PACKAGE_PIN N9  [get_ports {GPIO_tri_io[19]}]
set_property PACKAGE_PIN J13 [get_ports {GPIO_tri_io[20]}]
set_property PACKAGE_PIN H14 [get_ports {GPIO_tri_io[21]}]
set_property PACKAGE_PIN R10 [get_ports {GPIO_tri_io[22]}]
set_property PACKAGE_PIN M14 [get_ports {GPIO_tri_io[23]}]
set_property PACKAGE_PIN P15 [get_ports {GPIO_tri_io[24]}]
set_property PACKAGE_PIN M12 [get_ports {GPIO_tri_io[25]}]
set_property PACKAGE_PIN K13 [get_ports {GPIO_tri_io[26]}]
set_property PACKAGE_PIN R15 [get_ports {GPIO_tri_io[27]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_io*}]

set_property PACKAGE_PIN N12 [get_ports {CSI_C_N}]
set_property PACKAGE_PIN N11 [get_ports {CSI_C_P}]
set_property PACKAGE_PIN R8  [get_ports {CSI_D_N[0]}]
set_property PACKAGE_PIN R7  [get_ports {CSI_D_P[0]}]
set_property PACKAGE_PIN R13 [get_ports {CSI_D_N[1]}]
set_property PACKAGE_PIN R12 [get_ports {CSI_D_P[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {CSI_*}]
set_property PACKAGE_PIN N8  [get_ports {CLP_D_N[0]}]
set_property PACKAGE_PIN N7  [get_ports {CLP_D_P[0]}]
set_property PACKAGE_PIN P14 [get_ports {CLP_D_N[1]}]
set_property PACKAGE_PIN P13 [get_ports {CLP_D_P[1]}]
#set_property PACKAGE_PIN R11 [get_ports {CLP_C_N}]
#set_property PACKAGE_PIN P11 [get_ports {CLP_C_P}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_*}]
set_property PULLDOWN true [get_ports {CLP_*}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
create_clock -period 6.250 -name csi_clk -add [get_ports CSI_C_P]

Software Design - Vitis

For SDK project creation, follow instructions from:

Vitis

Application

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2018.3 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

• Modified Files: blconfig.h, bootloader.c
• Changes:
  
  • Add some console outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2018.3 xilisf_v5_11

• Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2018.3 FSBL

General:

• Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  
  • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
  • CPLD access
  • Read CPLD Firmware and SoC Type
  • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2018.3 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
• Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

1. :

   Code Block
   language bash theme Midnight
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. Press 0 and enter to start "Module Selection Guide"

3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

       Note
       Note: Select correct one, see also Vivado Board Part Flow

       
       

4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

   
   

5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

7. Copy PetaLinux build image files to prebuilt folder

   • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
     

     Info
     "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

     
     

     Page properties
     hidden true id Comments
     This step depends on Xilinx Device/Hardware for Zynq-7000 series copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ZynqMP copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ... ...

     
     

8. Generate Programming Files with Vitis

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
   TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

   
   

   Note
   TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

   
   

Launch

Programming

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Info
      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

      
      

QSPI-Boot mode

Boot.bin on QSPI Flash and image.ub and boot.scr on SD.

1. Connect USB Power In to get power on module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

3. 
   

   Code Block
   language bash theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0727 (optional)

   
   

   Note
   To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

   
   

4. Remove cable from USB Power In
5. Copy image.ub and boot.scr on SD
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
   • Important: Do not copy Boot.bin on SD (it is not used; see SD note), only other files.
6. Copy init.sh on SD
   • location: <project folder>/misc/sd/
7. Insert SD-Card in SD-Slot.
8. Connect USB Power In to get power on module

SD-Boot mode

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot (fsbl, u-boot) and SD for secondary boot (image.ub, boot.src)

JTAG

Not used on this Example.

Usage

1. Prepare HW like described in section Programming

2. Connect UART USB (most cases same as JTAG)

3. Insert SD Card with image.ub and boot.src

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   
   

4. Power On PCB

   Expand
   title boot process
   1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   
   

   Page properties
   hidden true id Comments
   This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ...

   
   

Linux

1. Open Serial Console (e.g. putty)

   1. Speed: 115200

   2. select COM Port

      Info
      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

      
      

2. Linux Console:
   

   Code Block
   language bash theme Midnight
   petalinux login: root Password: root

   
   

   Info
   Note: Wait until Linux boot finished

   
   

3. You can use Linux shell now.
   

   Code Block
   language bash theme Midnight
   i2cdetect -y -r 1 (check I2C (Bus 0...2 possible)) USB (insert USB device)

   
   

4. Camera stream will be enabled via init.sh script on SD

5. Take image from camera (must be enabled with init.sh script):
   

   Code Block
   language bash theme Midnight
   fbgrab -d /dev/fb0 /run/media/sda1/camera.png (write image to USB Stick)

   
   

System Design - Vivado

Block Design

PS Interfaces

Activated interfaces:

Constraints

Basic module constraints

#
# Common BITGEN related settings for TE0727 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Design specific constraint

#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

set_property PACKAGE_PIN G11 [get_ports {CEC_A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CEC_A[0]}]
set_property PACKAGE_PIN H13 [get_ports {HPD_A}]
set_property IOSTANDARD LVCMOS33 [get_ports {HPD_A}]
set_property PACKAGE_PIN G14 [get_ports {GLED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GLED[0]}]
set_property PACKAGE_PIN G12 [get_ports {IIC_A_scl_io}]
set_property PACKAGE_PIN H12 [get_ports {IIC_A_sda_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {IIC_A_*}]
set_property PACKAGE_PIN K12 [get_ports {CT_HPD[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CT_HPD[0]}]

set_property PACKAGE_PIN F12 [get_ports {HDMI_TXC_P}]
set_property PACKAGE_PIN E13 [get_ports {HDMI_TXC_N}]
set_property PACKAGE_PIN E11 [get_ports {HDMI_TX_P[0]}]
set_property PACKAGE_PIN E12 [get_ports {HDMI_TX_N[0]}]
set_property PACKAGE_PIN G15 [get_ports {HDMI_TX_P[1]}]
set_property PACKAGE_PIN F15 [get_ports {HDMI_TX_N[1]}]
set_property PACKAGE_PIN F14 [get_ports {HDMI_TX_N[2]}]
set_property PACKAGE_PIN F13 [get_ports {HDMI_TX_P[2]}]
set_property IOSTANDARD TMDS_33 [get_ports {HDMI_*}]

set_property PACKAGE_PIN J11 [get_ports {GPIO_tri_io[0]}]
set_property PACKAGE_PIN H11 [get_ports {GPIO_tri_io[1]}]
set_property PACKAGE_PIN J15 [get_ports {GPIO_tri_io[2]}]
set_property PACKAGE_PIN L15 [get_ports {GPIO_tri_io[3]}]
set_property PACKAGE_PIN N13 [get_ports {GPIO_tri_io[4]}]
set_property PACKAGE_PIN P8  [get_ports {GPIO_tri_io[5]}]
set_property PACKAGE_PIN M10 [get_ports {GPIO_tri_io[6]}]
set_property PACKAGE_PIN L12 [get_ports {GPIO_tri_io[7]}]
set_property PACKAGE_PIN M11 [get_ports {GPIO_tri_io[8]}]
set_property PACKAGE_PIN P10 [get_ports {GPIO_tri_io[9]}]
set_property PACKAGE_PIN P9  [get_ports {GPIO_tri_io[10]}]
set_property PACKAGE_PIN K15 [get_ports {GPIO_tri_io[11]}]
set_property PACKAGE_PIN M9  [get_ports {GPIO_tri_io[12]}]
set_property PACKAGE_PIN L13 [get_ports {GPIO_tri_io[13]}]
set_property PACKAGE_PIN L14 [get_ports {GPIO_tri_io[14]}]
set_property PACKAGE_PIN M15 [get_ports {GPIO_tri_io[15]}]
set_property PACKAGE_PIN J14 [get_ports {GPIO_tri_io[16]}]
set_property PACKAGE_PIN N14 [get_ports {GPIO_tri_io[17]}]
set_property PACKAGE_PIN K11 [get_ports {GPIO_tri_io[18]}]
set_property PACKAGE_PIN N9  [get_ports {GPIO_tri_io[19]}]
set_property PACKAGE_PIN J13 [get_ports {GPIO_tri_io[20]}]
set_property PACKAGE_PIN H14 [get_ports {GPIO_tri_io[21]}]
set_property PACKAGE_PIN R10 [get_ports {GPIO_tri_io[22]}]
set_property PACKAGE_PIN M14 [get_ports {GPIO_tri_io[23]}]
set_property PACKAGE_PIN P15 [get_ports {GPIO_tri_io[24]}]
set_property PACKAGE_PIN M12 [get_ports {GPIO_tri_io[25]}]
set_property PACKAGE_PIN K13 [get_ports {GPIO_tri_io[26]}]
set_property PACKAGE_PIN R15 [get_ports {GPIO_tri_io[27]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_io*}]

set_property PACKAGE_PIN N12 [get_ports {CSI_C_N}]
set_property PACKAGE_PIN N11 [get_ports {CSI_C_P}]
set_property PACKAGE_PIN R8  [get_ports {CSI_D_N[0]}]
set_property PACKAGE_PIN R7  [get_ports {CSI_D_P[0]}]
set_property PACKAGE_PIN R13 [get_ports {CSI_D_N[1]}]
set_property PACKAGE_PIN R12 [get_ports {CSI_D_P[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {CSI_*}]
set_property PACKAGE_PIN N8  [get_ports {CLP_D_N[0]}]
set_property PACKAGE_PIN N7  [get_ports {CLP_D_P[0]}]
set_property PACKAGE_PIN P14 [get_ports {CLP_D_N[1]}]
set_property PACKAGE_PIN P13 [get_ports {CLP_D_P[1]}]
#set_property PACKAGE_PIN R11 [get_ports {CLP_C_N}]
#set_property PACKAGE_PIN P11 [get_ports {CLP_C_P}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_*}]
set_property PULLDOWN true [get_ports {CLP_*}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
create_clock -period 6.250 -name csi_clk -add [get_ports CSI_C_P]

set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_N[1]}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_N[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_P[1]}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_P[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {CSI_D_P[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {CSI_D_P[0]}]

set_property PACKAGE_PIN P14 [get_ports {CLP_D_N[1]}]
set_property PACKAGE_PIN N8 [get_ports {CLP_D_N[0]}]
set_property PACKAGE_PIN P13 [get_ports {CLP_D_P[1]}]
set_property PACKAGE_PIN N7 [get_ports {CLP_D_P[0]}]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

fsbl

TE modified 2020.2 FSBL

General:

• Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c (for hooks and board)

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  
  • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
  • CPLD access
  • Read CPLD Firmware and SoC Type
  • Configure Marvell PHY

fsbl_flash

TE modified 2020.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0727

Hello TE0727 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• No changes

U-Boot

Start with petalinux-config -c u-boot
Changes:

• CONFIG_ENV_IS_NOWHERE=y

• # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

#include <configs/zynq-common.h>
#include <configs/platform-auto.h>

Device Tree

/include/ "system-conf.dtsi"
/ {
};
  
  
/ {
    #address-cells = <1>;
    #size-cells = <1>;
   
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
        // HDMI Output frame buffer
        hdmi_fb_reserved_region@1FC00000 {

TE modified 2018.3 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

SDK Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2019.2 FSBL

General:

• Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  • enable VTC and VDMA cores for camera access

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0727

Hello TE0727 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• No changes

U-Boot

Start with petalinux-config -c u-boot
Changes:

• CONFIG_ENV_IS_NOWHERE=y

• # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Device Tree

/include/ "system-conf.dtsi"
/ {
};
  
  
/ {
    #address-cells = <1>;
    #size-cells = <1>;
  
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
		// HDMI Output frame buffer
        hdmi_fb_reserved_region@1FC00000 {
            compatible = "removed-dma-pool";
            no-map;
            // 512M (M modules)
            reg = <0x1FC00000 0x400000>;
            // 128M (R modules)
            //reg = <0x7C00000 0x400000>;
        };
/*	// Use second frame buffer if you want separate area for camera image	
        camera_fb_reserved_region@1FC00000 {
            compatible = "removed-dma-pool";
            no-map;
            // 512M (M modules)
            reg = <0x1FC00000 0x400000>;
            // 128M (R modules)
            //reg = <0x7800000 0x400000>;
        };
*/  
    };
  
    hdmi_fb: framebuffer@0x1FC00000 {           // HDMI out
        compatible = "simple-framebuffer";
        // 512M (M modules)
        reg = <0x1FC00000 (1280 * 720 * 4)>;    // 720p
        // 128M (R modules)
        //reg = <0x7C00000 (1280 * 720 * 4)>;   // 720p
        width = <1280>;                         // 720p
        height = <720>;                       compatible  // 720p= "removed-dma-pool";
        stride = <(1280 * 4)>; no-map;
            // 512M (M modules)
   // 720p
        formatreg = <0x1FC00000 "a8b8g8r8"0x400000>;
        status = "okay";
    };
/*  // In128M "go through" mode only one framebuffer is used
(R modules)
        camera_fb: framebuffer@0x1FC00000 {  //reg = <0x7C00000 0x400000>;
    // CAMERA in
  };
/*  // Use second frame compatiblebuffer = "simple-framebuffer";
        // 512M (M modules)
if you want separate area for camera image  
        camera_fb_reserved_region@1FC00000 {
  reg = <0x1FC00000 (1280 * 720 * 4)>;   compatible // 720p
= "removed-dma-pool";
         // 128M (R modules) no-map;
        //reg = <0x7800000 (1280 *// 720512M *(M 4modules)>;
   // 720p
        widthreg = <1280><0x1FC00000 0x400000>;
            // 128M (R modules)
            //reg 720p
= <0x7800000 0x400000>;
      height = <720>};
*/ 
    };
   
    hdmi_fb: framebuffer@0x1FC00000 {           // 720pHDMI out
        stridecompatible = <(1280 * 4)>;"simple-framebuffer";
        // 512M         // 720p(M modules)
        formatreg = "a8b8g8r8";
    };
*/  
<0x1FC00000 (1280 * 720 * 4)>;     vcc_3V3: fixedregulator@0 {
// 720p
        // 128M compatible = "regulator-fixed";(R modules)
        regulator-name//reg = "vccaux-supply";
        regulator-min-microvolt = <3300000>;<0x7C00000 (1280 * 720 * 4)>;   // 720p
        regulator-max-microvoltwidth = <3300000>;
        regulator-always-on;
<1280>;     };
};
  
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";// 720p
    flash0: flash@0 {
  height = <720>;    compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells =// <1>;720p
        #size-cellsstride = <1>;
<(1280 * 4)>;        spi-max-frequency = <50000000>;
        partition@0x00000000// {720p
        format = "a8b8g8r8";
        labelstatus = "bootokay";
    };
/*  // In "go through" mode only regone =framebuffer <0x00000000is 0x00500000>;used
    camera_fb: framebuffer@0x1FC00000 {  };
       // partition@0x00500000CAMERA {in
            labelcompatible = "bootenvsimple-framebuffer";
        // 512M (M modules)
 reg = <0x00500000 0x00020000>;
    reg = <0x1FC00000 (1280 };
* 720 * 4)>;    // partition@0x00520000 {
   720p
         label = "kernel";
  // 128M (R modules)
        //reg = <0x00520000 0x00a80000>;
    <0x7800000 (1280 * 720 * 4)>;   // };720p
        partition@0x00fa0000width {
= <1280>;           label = "spare";
            reg// =720p
 <0x00fa0000 0x00000000>;
      height = };
<720>;        };
};
  
/*
* We need to disable Linux VDMA driver as VDMA
* already configured in FSBL
*/


&video_out_axi_vdma_0 {
	// Solution 1: Disable satandard VDMA driver (VDMA configuration should be done in the FSBL)
	status = "disabled";	
	// Solution 2: Configure VDMA using the custom driver (VDMA configuration in FSBL should be disabled)
    //compatible = "trenz,vdmafb   // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
    //width = <1280>;
    //height = <720>;
};
*/ 
    vcc_3V3: fixedregulator@0 {
      //stride = <(1280compatible * 4)>= "regulator-fixed";
    //format    regulator-name = "a8b8g8r8vccaux-supply";
};

&video_in_axi_vdma_0 {
	// Solution 1: Disable satandard VDMA driver (VDMA configuration should be done in the FSBL)
	status = "disabled";
};

&gpio0 {
    interrupt-controller        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        regulator-always-on;
    #interrupt-cells = <2>};
};
  
&qspi {
/* I2C1 */  
&i2c1 {
	#address-cells = <1>;
	    #size-cells = <0>;

	i2cmux: i2cmux@70  {
		    status = "okay";
    flash0: flash@0 {
        compatible = "nxpjedec,pca9540spi-nor";
		#address-cells = <1>;
		#size-cells = <0>;
		        reg = <0x70><0x0>;

		ID_I2C@0 {
			        #address-cells = <1>;
			        #size-cells = <0><1>;
			reg = <0>    };
		};
  
/*
* We need to disable Linux VDMA driver as VDMA
		CSI_I2C@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
	};

};
/* USB */  
  
  
  
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy"* already configured in FSBL
*/


&video_out_axi_vdma_0 {
	// Solution 1: Disable standard VDMA driver (VDMA configuration should be done in the FSBL)
	status = "disabled";	
	// Solution 2: Configure VDMA using the custom driver (VDMA configuration in FSBL should be disabled)
    //compatible = "trenz,vdmafb";
    //width = <1280>;
    //height = <720>;
    //stride = <(1280  #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus* 4)>;
    //format = "a8b8g8r8";
};

&video_in_axi_vdma_0 {
	// Solution 1: Disable satandard VDMA driver (VDMA configuration should be done in the FSBL)
	status = "disabled";
};

&gpio0 {
    interrupt-controller;
    }#interrupt-cells = <2>;
};
  
&usb0 {
/* I2C1 - for usb-phy = <&usb_phy0>;
} ;
  

Kernel

Start with petalinux-config -c kernel

Changes:

REV02 */ 
&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;

	i2cmux: i2cmux@70  {
		compatible = "nxp,pca9540";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		ID_I2C@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		CSI_I2C@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
	};
};



/* USB */  
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
  
&usb0 {
    usb-phy = <&usb_phy0>;
} ;

FSBL patch

Must be add manually, see template

Kernel

Start with petalinux-config -c kernel

Changes:

• CONFIG_FB_SIMPLE=y

• # CONFIG_FRAMEBUFFER_CONSOLE is not set

• CONFIG_SND_SIMPLE_CARD_UTILS=y
• CONFIG_SND_SIMPLE_CARD=y
• CONFIG_USBIP_CORE=y
• # CONFIG_USBIP_VHCI_HCD is not set
• # CONFIG_USBIP_HOST is not set
• # CONFIG_USBIP_VUDC is not set

Change linux-xlnx_%.bbappend:

FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"

SRC_URI += "file://devtool-fragment.cfg \
            file://0001-QSPI-s25fl127_8-2020_2.patch \
            "

• Add 0001-QSPI-s25fl127_8-2020_2.patch to "<project folder>\project-spec\meta-user\recipes-kernel\linux\linux-xlnx\"# CONFIG_USBIP_DEBUG is not set

Rootfs

Start with petalinux-config -c rootfs

Changes:

• CONFIG_i2c-tools

• alsa-plugins
• alsa-lib-dev
• libasound
• alsa-conf-base
• alsa-conf
• alsa-utils
• alsa-utils-aplay
• busybox-httpd

Applications

startup

Script App to load init.sh from SD Card if available.

• =y

• CONFIG_i2cpick=y
• CONFIG_util-linux-mount=y
• CONFIG_util-linux-umount=y

Applications

See "<project folder>See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files"

startup

Script App to load init.sh from SD Card if available.

rpicam

Application used to enable and configure Raspbery Pi camera module

See: \os\petalinux\project-spec\meta-user\recipes-apps\rpicam\files

fbgrab

Application used to take screenshot from camera

See: \os\petalinux\project-spec\meta-user\recipes-apps\fgrab

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

See: \os\petalinux\project-spec\meta-user\recipes-apps\webfwu\files

Kernel Modules

te-audio-codec

Simple module stab to use audio interface.

See: \os\petalinux\project-spec\meta-user\recipes-modules\te-audio-codec\files

Additional Software

No additional software is needed.

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices