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  • This line was added.
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  • Formatting was changed.


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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2023-12-143.1.17
  • updated according to Vivado 2023.2
ma
2023-06-133.1.16
  • Design flow:
    • added alternative programming files in Petalinux
  • added chapter FSBL Patch in Software Design - Petalinux
ma
2023-06-013.1.15
  • removed u-boot.dtb from Design flow
ma
2023-06-013.1.14
  • expandable lists for revision history and supported hardware
wh
2023-05-253.1.13
  • updated according to Vivado 2022.2
ma
2023-02-083.1.12
  • removed content of
    • Special FSBL for QSPI programming
ma
2022-08-243.1.11
  • Modification from link "available short link"
ma
2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
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        cellHighlightingtrue

        ExampleComment
        12



  • ...


Overview

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Notes :

Refer to http://trenz.org/te0818-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key features, which can be tested with the design


Excerpt
  • Vitis/Vivado 2023.2
  • TEBF0818
  • Linux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • RGPIO
  • Display Port (DP)
  • user LED access
  • Modified FSBL for Si5345 programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description
Expand
titleExpand List
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DateVivadoProject BuiltAuthorsDescription
2024-03-082023.2TE0818-StarterKit-vivado_2023.2-build_4_20240308103809.zip
TE0818-StarterKit_noprebuilt-vivado_2023.2-build_4_20240308103809.zip
Manuela Strücker
  • new assembly variants
2023-12-152023.2TE0818-StarterKit-vivado_2023.2-build_3_20231215122410.zip
TE0818-StarterKit_noprebuilt-vivado_2023.2-build_3_20231215122410.zip
Manuela Strücker
  • 2023.2 release
  • new assembly variants
2023-08-152022.2TE0818-StarterKit-vivado_2022.2-build_6_20230815120540.zip
TE0818-StarterKit_noprebuilt-vivado_2022.2-build_6_20230815120540.zip
Manuela Strücker
  • new assembly variants
2023-06-142022.2TE0818-StarterKit-vivado_2022.2-build_2_20230619104156.zip
TE0818-StarterKit_noprebuilt-vivado_2022.2-build_2_20230619104156.zip
Manuela Strücker
  • 2022.2 release
  • new assembly variants
2023-02-142021.2.1TE0818-StarterKit_noprebuilt-vivado_2021.2-build_20_20230214112518.zip
TE0818-StarterKit-vivado_2021.2-build_20_20230214112518.zip
Manuela Strücker
  • new assembly variants
2022-09-122021.2.1TE0818-StarterKit_noprebuilt-vivado_2021.2-build_15_20220912092618.zip
TE0818-StarterKit-vivado_2021.2-build_15_20220912092618.zip
Manuela Strücker
  • update board part files compatible to Vivado 2021.2.1
2022-05-122021.2TE0818-StarterKit_noprebuilt-vivado_2021.2-build_14_20220512120454.zip
TE0818-StarterKit-vivado_2021.2-build_14_20220512120454.zip
Manuela Strücker
  • new assembly variant
2022-02-242021.2TE0818-StarterKit_noprebuilt-vivado_2021.2-build_11_20220224094436.zip
TE0818-StarterKit-vivado_2021.2-build_11_20220224094436.zip
Manuela Strücker
  • bugfix (read MAC from EEPROM)
2022-02-032021.2

TE0818-StarterKit_noprebuilt-vivado_2021.2-build_11_20220203074431.zip
TE0818-StarterKit-vivado_2021.2-build_11_20220203074431.zip

John Hartfiel
  • initial release



Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if issue fixed


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IssuesDescriptionWorkaroundTo be fixed version
Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--
MAC from EEPROM

The MAC address stored in the EEPROM is not read out and initialised correctly during start-up.
This is caused by two I2C expanders each switched to the same EEPROM with the same address
i2cswitch@73 --> i2c@5 --> reg = <0x50> and
i2cswitch@77 --> i2c@4 --> reg = <0x50>

Switching the second I2C expander (i2cswitch@77) to another channel in the fsbl solves the error during the start-up procedure.Solved with 20220224 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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SoftwareVersionNote
Vitis2023.2needed, Vivado is included into Vitis installation
PetaLinux2023.2needed
Skyworks ClockBuilder Pro---

optional

Info

Si5345A-B-GM is no longer supported by the latest Skyworks ClockBuilder Pro software.



Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0818-01-9BE21-A9eg_1e_4gbREV014GB128MBNANANA
TE0818-01-9BE21-AZ9eg_1e_4gbREV014GB128MBNANANA
TE0818-01-9BI41-X9eg_1i_8gbREV018GB128MBNANANA
TE0818-01-9GI21-A*9eg_2i_4gbREV014GB128MBNANANA
TE0818-01-9GI21-AK9eg_2i_4gbREV014GB128MBNANANA
TE0818-01-9GI81-A9eg_2i_4gbREV014GB128MBNANANA
TE0818-01-9GI81-AK9eg_2i_4gbREV014GB128MBNANANA
TE0818-01-BBE21-A15eg_1e_4gbREV014GB128MBNANANA
TE0818-01-BBE21-AZ15eg_1e_4gbREV014GB128MBNANANA
TE0818-01-BBE81-A15eg_1e_4gbREV014GB128MBNANANA
TE0818-01-BBE81-AK15eg_1e_4gbREV014GB128MBNANANA
TE0818-01-S0016eg_1e_4gbREV014GB128MBNANAwithout PLL
TE0818-01-S0029eg_2i_4gbREV014GB128MBNANANA
TE0818-01-S0039eg_2i_4gbREV014GB128MBNANANA
TE0818-01-T001K15eg_1e_4gbREV014GB128MBNANANA
TE0818-01-T002K9eg_2i_4gbREV014GB128MBNANANA
TE0818-02-6BE81-A6eg_1e_4gbREV024GB128MBNANANA
TE0818-02-6BE81-AK6eg_1e_4gbREV024GB128MBNANANA
TE0818-02-9BE81-A9eg_1e_4gbREV024GB128MBNANANA
TE0818-02-9BE81-AK9eg_1e_4gbREV024GB128MBNANANA
TE0818-02-9GI81-A9eg_2i_4gbREV024GB128MBNANANA
TE0818-02-9GI81-AK9eg_2i_4gbREV024GB128MBNANANA
TE0818-02-BBE81-A15eg_1e_4gbREV024GB128MBNANANA
TE0818-02-BBE81-AK15eg_1e_4gbREV024GB128MBNANANA
TE0818-02-BGI81-A15eg_2i_4gbREV024GB128MBNANANA
TE0818-02-BGI81-AK15eg_2i_4gbREV024GB128MBNANANA
TE0818-02-S0029eg_1i_8gbREV028GB128MBNANANA

*used as reference

Note: Design contains also Board Part Files for TE0818 only configuration, this board part files are not used for this reference design.


Design supports following carriers:

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Carrier ModelNotes
TEBF0818*
TEBT0818

*used as reference


Additional HW Requirements:

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Additional HardwareNotes
Display Port Monitor

Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL U2412M

USB KeyboardOptional HW
Can be used to get access to console which is show on Display Port
USB StickOptional HW
USB was tested with USB memory stick
SATA DiskOptional HW
PCIe CardOptional HW
ETH cableOptional HW
Ethernet works with DHCP, but can be setup also manually
SD cardwith fat32 partition

*used as reference

Content

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Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

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TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration


Additional Sources

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TypeLocationNotes
SI5345<project folder>\misc\PLL\

SI5345 Project with current PLL Configuration

Info

Si5345A-B-GM is no longer supported by the latest Skyworks Clockbuilder Pro software.



init.sh<project folder>\misc\sd\Additional Initialization Script for Linux


Prebuilt

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Notes :

  • prebuilt files
  • Template Table:

    • Scroll Title
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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Script-File*.scr

Distro Boot Script file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Note

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    Code Block
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    themeMidnight
    title_create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"
  3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note

      Note: Select correct one, see also Vivado Board Part Flow

      Important: Use Board Part Files, which ends with *_tebf0818


  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    Code Block
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    titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt


    Info

    Using Vivado GUI is the same, except file export to prebuilt folder.


  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Generate Programming Files with Vitis
    1. Copy PetaLinux build image files to prebuilt folder
      • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
        Info

        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

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        This step depends on Xilinx Device/Hardware

        for Zynq-7000 series

        • copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ZynqMP

        • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for Microblaze

        • ...
    2. Generate Programming Files

      Code Block
      languagepy
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      titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      Note

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

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Note:

  • Programming and Startup procedure

For basic board setup, LEDs... see: TEBF0818 Getting Started

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Info

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

Option for Boot.bin on QSPI Flash

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    Code Block
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    titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp hello_te0818


  3. Set Boot Mode to QSPI-Boot.
    • Depends on Carrier, see carrier TRM.
    • TEBF0818 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area

SD-Boot mode

  1. Copy image.ub, boot.src and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this example.


Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Info

    Note: See TRM of the Carrier, which is used.


    Tip

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr


  4. (Optional with TEBF0818) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
  5. (Optional with TEBF0818) Connect SATA Disc
  6. (Optional with TEBF0818) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
  7. (Optional with TEBF0818) Connect Network Cable
  8. Power On PCB

    Expand
    titleboot process

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


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    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for ZynqMP???

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for Microblaze with Linux

    1. FPGA Loads Bitfile from Flash,

    2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

    3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

    4. U-boot loads Linux from QSPI Flash into DDR


    for native FPGA

    ...



Linux

  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Info

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


  2. Linux Console:

    Code Block
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    themeMidnight
    # password disabled
    petalinux login: root
    Password: root


    Info

    Note: Wait until Linux boot finished


  3. You can use Linux shell now.

    Code Block
    languagebash
    themeMidnight
    i2cdetect -y -r 0	(check I2C 0 Bus, replace 0 with other bus number is also possible)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
    lspci               (PCIe check)


  4. Option Features

    • Webserver to get access to ZynqMP
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequency...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:

    • Set Enable to send Write date over RGPIO interface. 
  • Control:
    • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
    • CAN_S
Scroll Title
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titleVivado Hardware Manager



System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

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titlePS Interfaces

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TypeNote
DDR
QSPIMIO
SD0MIO
SD1MIO
CAN0EMIO
I2C0MIO
PJTAG0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO/GTP
PCIeMIO/GTP
SATAGTP
Display PortEMIO/GTP


Constraints

Basic module constraints

Code Block
languageruby
title_i_bitgen.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constraints

Code Block
languageruby
title_i_io.xdc
#System Controller IP
#LED_HD SC0 J3:C13
#LED_XMOD SC17 J3:B19 
#CAN RX SC19 J3:B23 
#CAN TX SC18 J3:B22  
#CAN S  SC16 J3:B18 


#HDIO_SC0    J14
set_property PACKAGE_PIN J14 [get_ports BASE_sc0]
#HDIO_SC5    G13
set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
#HDIO_SC6    J15
set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
#HDIO_SC7    K15
set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
#HDIO_SC10   A15
set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
#HDIO_SC11   B15
set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
#HDIO_SC12   C13
set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
#HDIO_SC13   C14
set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
#HDIO_SC14   E13
set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
#HDIO_SC15   E14
set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
#HDIO_SC16   A13
set_property PACKAGE_PIN A13 [get_ports BASE_sc16]
#HDIO_SC17   B13
set_property PACKAGE_PIN B13 [get_ports BASE_sc17]
#HDIO_SC18   A14
set_property PACKAGE_PIN A14 [get_ports BASE_sc18]
#HDIO_SC19   B14
set_property PACKAGE_PIN B14 [get_ports BASE_sc19]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]


# Audio Codec
#LRCLK		  J3:49 B47_L9_N
#BCLK		  J3:51 B47_L9_P
#DAC_SDATA	J3:53 B47_L7_N
#ADC_SDATA	J3:55 B47_L7_P

#LRCLK G14
set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ]
#BCLK G15
set_property PACKAGE_PIN G15 [get_ports I2S_bclk ]
#DAC_SDATA E15
set_property PACKAGE_PIN E15 [get_ports I2S_sdin ]
#ADC_SDATA F15
set_property PACKAGE_PIN F15 [get_ports I2S_sdout ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]

# MGTs
#   F25  MGT_128_CLK0_P -> U5,45 -> Si5345 -> out6
#   F26  MGT_128_CLK0_N -> U5,44 -> Si5345 -> out6
#   D25  MGT_128_CLK1_P -> B2B,J2-A7 -> floating
#   D26  MGT_128_CLK1_N -> B2B,J2-A6 -> floating

#   R8   MGT_228_CLK0_P -> B2B,J3-B27 -> TEBF0818-01_FMC_J5E-D5
#   R7   MGT_228_CLK0_N -> B2B,J3-B26 -> TEBF0818-01_FMC_J5E-D4
#   N8   MGT_228_CLK1_P -> U5,35 -> Si5345 -> out3
#   N7   MGT_228_CLK1_N -> U5,34 -> Si5345 -> out3

#   L8   MGT_229_CLK0_P -> B2B,J3-C26 -> TEBF0818-01_FMC_J5E-B21
#   L7   MGT_229_CLK0_N -> B2B,J3-C25 -> TEBF0818-01_FMC_J5E-B20
#   J8   MGT_229_CLK1_P -> U5,31 -> Si5345 -> out2
#   J7   MGT_229_CLK1_N -> U5,30 -> Si5345 -> out2

#   G8   MGT_230_CLK0_P -> U5,28 -> Si5345 -> out1
#   G7   MGT_230_CLK0_N -> U5,27 -> Si5345 -> out1
#   E8   MGT_230_CLK1_P -> B2B,J3-D27 -> TEBF0818-01_CLK7_P -> B2B,J2-D5 -> U5,51 -> Si5345 -> out7
#   E7   MGT_230_CLK1_N -> B2B,J3-D26 -> TEBF0818-01_CLK7_N -> B2B,J2-D6 -> U5,50 -> Si5345 -> out7

set_property PACKAGE_PIN F25 [get_ports {MGT_CLK_IN_clk_p[0]}]
set_property PACKAGE_PIN D25 [get_ports {MGT_CLK_IN_clk_p[1]}]
set_property PACKAGE_PIN R8  [get_ports {MGT_CLK_IN_clk_p[2]}]
set_property PACKAGE_PIN N8  [get_ports {MGT_CLK_IN_clk_p[3]}]
set_property PACKAGE_PIN L8  [get_ports {MGT_CLK_IN_clk_p[4]}]
set_property PACKAGE_PIN J8  [get_ports {MGT_CLK_IN_clk_p[5]}]
set_property PACKAGE_PIN G8  [get_ports {MGT_CLK_IN_clk_p[6]}]
set_property PACKAGE_PIN E8  [get_ports {MGT_CLK_IN_clk_p[7]}]  

Software Design - Vitis

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Note:
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  • sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2023.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2023.2 xilisf_v5_11

  • Changed default Flash type to 5.


----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY


----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name


Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5345 Configuration
    • OTG+PCIe Reset over MIO
    • I2C MUX for EEPROM MAC

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0818

Hello TE0818 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • select SD default instead of eMMC:
    • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
  • add new flash partition for bootscr and sizing
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
  • Identification
    • CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
    • CONFIG_SUBSYSTEM_PRODUCT="TE0818_TEBF0818"

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • MAC from eeprom together with uboot and device tree settings:
    • CONFIG_ENV_OVERWRITE=y
    • CONFIG_NET_RANDOM_ETHADDR is not set
  • Boot Modes:
    • CONFIG_QSPI_BOOT=y
    • CONFIG_SD_BOOT=y
    • CONFIG_ENV_IS_IN_FAT is not set
    • CONFIG_ENV_IS_IN_NAND is not set
    • CONFIG_ENV_IS_IN_SPI_FLASH is not set
    • CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
    • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
  • Identification
    • CONFIG_IDENT_STRING=" TE0818_TEBF0818"


Change platform-top.h:

Code Block
languagejs
#no changes

Device Tree

Code Block
languagejs
titleproject-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi
 /include/ "system-conf.dtsi"


/*------------------ gtr --------------------*/

//https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver

/ {
  refclk3:psgtr_dp_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <27000000>;
  };

  refclk2:psgtr_pcie_usb_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <100000000>;
  };

  refclk1:psgtr_sata_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <150000000>;
  };

  //refclk0:psgtr_unused_clock {
  //        compatible = "fixed-clock";
  //        #clock-cells = <0x00>;
  //        clock-frequency = <100000000>;
  //};
};

&psgtr {
  clocks = <&refclk1 &refclk2 &refclk3>;
  /* ref clk instances used per lane */
  clock-names = "ref1\0ref2\0ref3";
};



/*------------------ SD --------------------*/
&sdhci0 {
    // disable-wp;
    no-1-8-v;
};

&sdhci1 {
    // disable-wp;
    no-1-8-v;
};


/*------------------- USB --------------------*/
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    snps,usb3_lpm_capable;
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    phy-names = "usb2-phy","usb3-phy";
    maximum-speed = "super-speed";
};


/*------------------ ETH PHY --------------------*/
&gem3 {
    /delete-property/ local-mac-address;
    phy-handle = <&phy0>;

    nvmem-cells = <ð0_addr>;
    nvmem-cell-names = "mac-address";

    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};



/*----------------- SATA PHY --------------------*/
&sata {

     ceva,p0-burst-params = <0x13084a06>;
     ceva,p0-cominit-params = <0x18401828>;
     ceva,p0-comwake-params = <0x614080e>;
     ceva,p0-retry-params = <0x96a43ffc>;
     ceva,p1-burst-params = <0x13084a06>;
     ceva,p1-cominit-params = <0x18401828>;
     ceva,p1-comwake-params = <0x614080e>;
     ceva,p1-retry-params = <0x96a43ffc>;

};


/*-------------------- QSPI ---------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        
        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        spi-max-frequency = <90000000>;
    };
};


/*------------------ I2C --------------------*/
&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c-mux-idle-disconnect;
        i2c@0 { // MCLK TEBF0818 SI5338A, 570FBB000290DG_unassembled
            reg = <0>;
        };
        i2c@1 { // SFP TEBF0818 PCF8574DWR
            reg = <1>;
        };
        i2c@2 { // PCIe
            reg = <2>;
        };
        i2c@3 { // SFP1 TEBF0818
            reg = <3>;
        };
        i2c@4 {// SFP2 TEBF0818
            reg = <4>;
        };
        i2c@5 { // TEBF0818 EEPROM
            reg = <5>;
            eeprom: eeprom@50 {
                compatible = "microchip,24aa025", "atmel,24c02";
                reg = <0x50>;
                
                #address-cells = <1>;
                #size-cells = <1>;
                eth0_addr: eth-mac-addr@FA {
                  reg = <0xFA 0x06>;
                };
            };
        };
        i2c@6 { // TEBF0818 FMC
            reg = <6>;
        };
        i2c@7 { // TEBF0818 USB HUB
            reg = <7>;
        };
    };
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        reg = <0x77>;
        i2c-mux-idle-disconnect;
        i2c@0 { // TEBF0818 PMOD P1
            reg = <0>;
        };
        i2c@1 { // i2c Audio Codec
            reg = <1>;
            /*
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
            };
            */
        };
        i2c@2 { // TEBF0818 Firefly A
            reg = <2>;
        };
        i2c@3 { // TEBF0818 Firefly B
            reg = <3>;
        };
        i2c@4 { //Module PLL Si5338 or SI5345
            reg = <4>;
        };
        i2c@5 { //TEBF0818 CPLD
            reg = <5>;
        };
        i2c@6 { //TEBF0818 Firefly PCF8574DWR
            reg = <6>;
        };
        i2c@7 { // TEBF0818 PMOD P3
            reg = <7>;
        };
    };
};

Kernel

Start with petalinux-config -c kernel

Changes:

  • Only needed to fix JTAG Debug issue:
    • # CONFIG_CPU_FREQ is not set
  • Support PCIe memory card
    • CONFIG_NVME_CORE=y
    • CONFIG_BLK_DEV_NVME=y
    • # CONFIG_NVME_MULTIPATH is not set
    • # CONFIG_NVME_VERBOSE_ERRORS is not set
    • # CONFIG_NVME_HWMON is not set
    • # CONFIG_NVME_AUTH is not set
    • CONFIG_NVME_TARGET=y
    • # CONFIG_NVME_TARGET_PASSTHRU is not set
    • # CONFIG_NVME_TARGET_LOOP is not set
    • # CONFIG_NVME_TARGET_FC is not set
    • # CONFIG_NVME_TARGET_TCP is not set
    • # CONFIG_NVME_TARGET_AUTH is not set
    • CONFIG_SATA_AHCI=y
    • CONFIG_SATA_MOBILE_LPM_POLICY=0

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • For web server app:
    • CONFIG_busybox-httpd=y
  • For additional test tools only:
    • CONFIG_i2c-tools=y
    • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
  • For auto login:
    • CONFIG_imagefeature-serial-autologin-root=y

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Note

te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src"


Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for ZynqMP access. Need busybox-httpd


Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

SI5345

File location "<project folder>\misc\PLL\Si5345_*\Si5345-*.slabtimeproj"

General documentation how you work with this project will be available on Si5345

Info

Si5345A-B-GM is no longer supported by the latest Skyworks Clockbuilder Pro software.


App. A: Change History and Legal Notices

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Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


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DateDocument Revision

Authors

Description

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typeFlat

  • new assembly variants
2023-12-18v.22Thomas Friedrich
  • 2023.2 release
  • new assembly variants
2023-06-21v.16Manuela Strücker
  • 2022.2 release
  • new assembly variants
2023-04-13v.14Manuela Strücker
  • new assembly variants
2022-11-21v.11Manuela Strücker
  • update board part files compatible to Vivado 2021.2.1
2022-09-06v.9Manuela Strücker
  • new assembly variant
2022-03-10v.6Manuela Strücker
  • update chapter QSPI-Boot mode
  • update chapter Usage
  • update SI5345
2022-02-24v.3Manuela Strücker
  • bugfix (read MAC from EEPROM)
2022-02-03v.2John Hartfiel
  • initial release
--all

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