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Possible race condition during power up
S1B and S1A both set to on can lead to a race condition. When Bitgen option "reset_on_error" is not set, the module does not boot.
Explanation
When S1B switch is ON, FPGA and FX2 start at the same time and as S1A is also ON, FX2 runs custom firmware which initializes SPI and trying to switch ON FPGA power (which is already forced to ON by S1B). So FX2 create error during FPGA load. As "reset_on_error" is not set FPGA will not try to boot again.
Solutions
1. If you don't use our USB API, switch S1A to OFF (S1B to ON). This way you disable FX2 activity on SPI bus and FPGA will boot from SPI by power on. (Fastest boot)
2. If you need USB API.
- Switch S1B to OFF. This way FX2 will control FPGA power and FPGA will start boot only after FX2 initialization
- Enable "reset_on_error" option for bootstream generation. This way, even if S1B is on and FX2 SPI init and FPGA boot will be in the same time (and bitstream will be corrupted during transfer by SPI) FPGA will reboot again if error occur.
Init and boot time depend on board capacitance and power supply so may vary from board to board, which affect to boot behavior.
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date
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author
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description
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0.01
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10/07/11
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AIK
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Release.
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0.02
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10/08/11
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AIK
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Added block diagram and few sections.
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0.03
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10/10/11
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AIK
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Added USB controller section with pin-out.
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0.04
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12.10.11
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FDR
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First general review.
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0.05
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10/13/11
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AIK
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Fixes after review. Add power diagram.
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0.06
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10/17/11
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AIK
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Add USB driver section.
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0.07
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10/17/11
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AIK
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Additions to configuration section.
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0.08
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11/16/11
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AIK
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Added module photos.
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0.09
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11/17/11
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AIK
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Net length information.
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0.10
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11/21/11
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AIK
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TE0300 compatibility information
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0.11
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11/22/11
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AIK
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Additional information to compatibility chapter
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0.12
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11/30/11
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AIK
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Added eFUSE programming section
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0.13
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12/01/11
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AIK
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Adder board revision and assembly variant chapter
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0.14
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01/20/12
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AIK
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Added pin compatibility note and manual reference.
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0.15
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01/25/12
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AIK
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Added R102 R103 location image. Added Appendix A.
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0.16
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02/16/12
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AIK
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Module options chapter
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0.17
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09/05/12
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AIK
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Fixed JTAG Vref
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0.18
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09/12/12
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AIK
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Fixed net length table
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0.19
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11/27/12
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AIK
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Fixed J4 user pin count
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0.20
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03/13/13
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AIK
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Fixed Table 7
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0.21
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03.07.13
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AIK
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Fixed pin count
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