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Reason: Power Handling Improvement

Impact: None. Voltage supply monitoring leads to resets.Voltages are monitored and if out of range reset is triggered.

#5 Added diode D3 between signals "INIT" and "PROG_B".

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• New CBP version (4.6) is used which leads to MultiSynth parameter changes.
• Enable optional FPGA Fabric clock CLK0 100 MHz with LVDS.
• Enable clock CLK1 50 MHz with two single ended (Port A and B) CMOS in phase clocks instead of one (Port A) used for ETH PHY syncronisation.

Type: Schematic Firmware Change

Reason: Improved PLL settings.

Impact: NoneTwo additional clocks are availabe. Settings are saved in NVM. Minor changes in electrical characteristics.

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