Page History
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Feature Summary
- Power Management
- JTAG
- Boot Mode
- LED
Firmware Revision and supported PCB Revision
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| Name / opt. VHD Name | Direction | Pin | Description | |||
|---|---|---|---|---|---|---|
| BOOTMODE_1 / MIO5 | out | 21 | Boot Mode Pin MIO5 | |||
| EN_PL | out | 23 | PL Power | |||
| F_TCK / C_TCK | out | 8 | JTAG FPGA | |||
| F_TDI / C_TDI | out | 10 | JTAG FPGA | |||
| F_TDO / C_TDO | in | 11 | JTAG FPGA | |||
| F_TMS / C_TMS | out | 9 | JTAG FPGA | |||
| I2C_SCL / SCL | in | 17 | I2C Bus from SoC to RTC and PLL/ currently_not_used | |||
| I2C_SDA / SDA | in | 16 | I2C Bus from SoC to RTC and PLL/ currently_not_used | |||
| JTAG_EN | in | 26 | nable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) | |||
| MIO0 | in | 14 | also connected to B2B / currently_not_used | |||
| MIO8 | in | 13 | external pullup, |
Functional Description
JTAG
Power
LED
| for status | |||
| PS_RST / SRST | in | 12 | B2B PS Reset to SoC |
| PWR_PL_OK / PL_PWR_OK | in | 27 | Power Good / currently_not_used |
| PWR_PS_OK / PS_PWR_OK | in | 28 | Power Good / currently_not_used |
| RST_IN_N / RESIN | in | 25 | B2B Main Reset to U41 |
| RTC_INT / RTC_INT | in | 4 | RTC / currently_not_used |
| Serialnumber | 20 | / currently_not_used | |
| TCK / M_TCK | in | 30 | JTAG B2B |
| TDI / M_TDI | in | 32 | JTAG B2B |
| TDO / M_TDO | out | 1 | JTAG B2B |
| TMS /M_TMS | in | 29 | JTAG B2B |
| LED | out | 5 | LED |
Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B J1-148(JTAG_EN).
Boot Mode
MIO5 is set constant to 1. Boot mode can be changed between QSPI or SD with B2B J2-133 Pin (BOOTMODE).
| J2-133 | Value | Description |
|---|---|---|
| GND | QSPI | default with external pull-down |
| VDD | SD |
JTAG only will be possible with other CPLD Firmware, but this is normally not needed.
Power
PL Power is enabled.
LED
| Status | Description |
|---|---|
| ON | if RSIN or SRST or MIO8 is zero |
| Blinking | all other states |
Appx. A: Change History and Legal Notices
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV01 | REV02, REV01 |
| Work in progressREV01 , Firmware released 2016-05-30 | ||||||||||||||||||||||
| 2018-03-07 | v.1 |
| Initial release | ||||||||||||||||||||||||
| All |
|
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