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#1 Changed R95 from 0Ohm to 2.2kOhm and C13 from 10nF to 100nF

Type: BOM change

Reason: 3V3_PER rail can be disabled/enabled via attached FPGA/SoC module using a RGPIO IP core to communicate with CPLD on TEF1002. If this function is used, enabling can lead to a reset of the module. This is due to a large inrush current, which is disturbing the module power supply. To prevent this the rise time is enlarged.

Impact: With new resistor and capacitor values the calculated 10%-90% rise time of Q4 is 0.4ms.

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