Page History

Overview

ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0821-info

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

8GB        

2.5 mm connectors        

64GB       

8GB        

^*used as reference

Design supports following carriers:

Carrier Model

Notes

TE0701

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

TE0703^*

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 cm carriers    

• Used as reference carrier.

TE0705

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

TE0706

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

TEBA0841

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

• No SD Slot available, pins goes to Pin Header

• For TEBA0841 REV01, please contact TE support

Design supports following carriers:

^*used as reference

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - AMD devices

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Prebuilt

Additional Sources

Notes :

Template Table:

Prebuilt

File

File-Extension

Description

BIF-File

*.bif

File with description to generate Bin-File

BIN-File

*.bin

Flash Configuration File with Boot-Image (Zynq-FPGAs)

BIT-File

*.bit

FPGA (PL Part) Configuration File

Distro Boot Script file

DebugProbes-File

*.ltx

Definition File for Vivado/Vivado Labtools Debugging Interface

Diverse Reports

---

Report files in different formats

LabTools Project-File

*.lpr

Vivado Labtools Project File

OS-Image

*.ub

Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

Software-Application-File

*.elf

Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0821 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides

• Vivado Projects - TE Reference Design

• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. Press 0 and enter to start "Module Selection Guide"

3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see also Vivado Board Part Flow

     
     

4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

   
   

5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart

   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

7. Generate Programming Files with Vitis (recommended)
   1. Copy PetaLinux build image files to prebuilt folder

      • copy u-boot.elf,

   u-boot.

   1. • system.dtb,

   system

   1. • bl31.

   dtb

   1. • elf, image.ub

   , bl31.elf

   1. • and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
        

        Info
        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

        
        

        Page properties
        hidden true id Comments
        This step depends on Xilinx Device/Hardware for Zynq-7000 series copy u-boot.elf,

   u-boot.dtb,

   1. • system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ZynqMP copy u-boot.elf,

   u-boot.dtb,

   1. • system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for Microblaze ...

   Generate

   1. • 
        

   2. Generate Programming Files with Vitis

      Code Block
      language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

      
      

      Note
      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

      
      

8. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell

2. Press 0 and enter to start "Module Selection Guide"

   1. Select assembly version

   2. Validate selection

   3. Select Create and open delivery binary folder

      Info
      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

      
      

QSPI-Boot mode

      Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0821 (optional)

   
   

   Note
   To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

   
   

3. Copy image.ub and boot.scr on SD or USB

   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries

   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"

4. Set Boot Mode to QSPI-Boot and insert SD or USB.

   • Depends on Carrier, see carrier TRM.

SD-Boot mode

Use this description for CPLD Firmware with SD Boot selectable.

1. Copy image.ub, boot.src and Boot.bin on SD

   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries

   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"

2. Set Boot Mode to SD-Boot.

   • Depends on Carrier, see carrier TRM.

3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming

2. Connect UART USB (most cases same as JTAG)

3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)

   Info
   Note: See TRM of the Carrier, which is used.

   
   

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   
   

4. Power On PCB

   Expand
   title boot process
   1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD/QSPI Flash into OCM 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   
   

Linux

1. Open Serial Console (e.g. putty)

   1. Speed: 115200

   2. Select COM Port
      

      Info
      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

      
      

2. Linux Console:
   

   Code Block
   language bash theme Midnight
   # password default disabled with 2021.2 petalinux release petalinux login: root Password: root

   
   

   Info
   Note: Wait until Linux boot finished

   
   

3. You can use Linux shell now.
   

   Code Block
   language bash theme Midnight
   i2cdetect -y -r 0 (check I2C 0 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check)

   
   

4. Option Features

   • Webserver to get access to Zynq

     • insert IP on web browser to start web interface

   • init.sh scripts

     • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

   
   

Vivado HW Manager

Monitoring:

• SI5338_CLK0 Counter:

  • Set radix from VIO signals to unsigned integer.
    Note: Frequency Counter is inaccurate and displayed unit is Hz for CLK signals

• SI5338 CLK1 is configured to 200MHz by default and SI5338 CLK3 is configured to 125MHz by default.

Control:

• Simple loopback vio_test_in test_out

• LED over X0/X1 , see TE0821 CPLD#LED

System Design - Vivado

Block Design

PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

set_property PACKAGE_PIN E5 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property PACKAGE_PIN C3 [get_ports {SI5338_CLK3_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK3_D_clk_p[0]}]

set_property PACKAGE_PIN B1 [get_ports {x0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
set_property PACKAGE_PIN C1 [get_ports {x1[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]

set_property PACKAGE_PIN G8 [get_ports {PHY_LED[0]}]
set_property PACKAGE_PIN E9 [get_ports {PHY_LED[1]}]
set_property PACKAGE_PIN D9 [get_ports {PHY_LED[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {PHY_LED[*]}]

set_property PACKAGE_PIN A5 [get_ports {TEST_IN[0]}]
set_property PACKAGE_PIN B6 [get_ports {TEST_OUT[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {TEST_IN[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {TEST_OUT[0]}]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

zynqmp_fsbl

TE modified 20212022.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_

pmufw

Xilinx default PMU firmware.

hello

TE modified 2021.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0821

Hello TE0821 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• select SD default instead of eMMC:
  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
  generate u-boot.dtb:
  •  CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
• add new flash partition for bootscr and sizing
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x2000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x20000000x40000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000

U-Boot

• Identification
  • CONFIG_SUBSYSTEM_HOSTNAME="trenz"
  • CONFIG_SUBSYSTEM_PRODUCT="TE0821"

U-Boot

Start with petalinux-config -c u-boot
Changes:

•  MAC MAC from eeprom together with uboot and device tree settings:
  • CONFIG_ENV_OVERWRITE=y
  • CONFIG_ZYNQ_GEMMAC_I2C_MAC_OFFSET=0xFAIN_EEPROM is not set
  • CONFIG_SYSNET_I2C_EEPROM_ADDR=0x50RANDOM_ETHADDR is not set
• Boot Modes:
  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • CONFIG_ENV_IS_IN_FAT is not set
  • # CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_ENV_IS_IN_SPI_FLASH is not set
  • CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x4040000
• Identification
  • CONFIG_IDENT_STRING=" TE0821"

Change platform-top.h:

#include <configs/xilinx_zynqmp.h>
#no changes

Device Tree

/include/ "system-conf.dtsi"


/*------------------------- QSPI -- SD1 sd2.0 ----------------------- */
&qspisdhci1 {
    #address-cells = <1>;
    #size-cells = <0>;disable-wp;
    no-1-8-v;
};


/*----------------------- USB 2.0 only --------------------*/
&dwc3_0 {
    status = "okay";
    flash0: flash@0 {dr_mode = "host";
        //compatible maximum-speed = "flash name, "micron,m25p80"high-speed";
    /delete-property/phy-names;
    compatible = "jedec,spi-nor"/delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
    reg = <0x0>snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
};

&usb0 {
    #address-cellsstatus = <1>"okay";
    /delete-property/ clocks;
    #size-cells/delete-property/ clock-names;
    clocks = <1><0x3 0x20>;
    }clock-names = "bus_clk";
};


/*------------------------- SD1ETH sd2.0PHY -----------------------*/
&sdhci1gem3 {
    disable-wp /delete-property/ local-mac-address;
    no-1-8-v;
};


/*------------------------- ETH PHY -----------------------*/
&gem3 {
    phy-handle = <&phy0>;
    
    nvmem-cells = <&eth0_addr>;
    nvmem-phy-handle = <&phy0>;
    
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";
    
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};


/*------------------------- USB 2.0 only QSPI ----------------------*/--- */
&dwc3_0qspi {
    status#address-cells = "okay"<1>;
    dr_mode#size-cells = "host"<0>;
    maximum-speedstatus = "high-speedokay";
    /delete-property/phy-names;
    /delete-property/phys;
flash0: flash@0 {
      /delete-property/snps,usb3_lpm_capable;
  compatible = snps,dis_u2_susphy_quirk"jedec,spi-nor";
     snps,dis_u3_susphy_quirk;
};
   reg 
&usb0 {= <0x0>;
    status = "okay";
  #address-cells  /delete-property/ clocks= <1>;
    /delete-property/ clock-names;
    clocks#size-cells = <0x3 0x20><1>;
    clock-names = "bus_clk"};
};


/*---------------------------- I2C ------------------------*/
&i2c0 {
    eeprom: eeprom@50 {
        compatible = "microchip,24aa025", "atmel,24c02";
        reg = <0x50>;
        
        #address-cells = <1>;
        #size-cells = <1>;
        eth0_addr: eth-mac-addr@FA {
          reg = <0xFA 0x06>;
     };     };
     
  };
};
    

/include/ "system-conf.dtsi"


/*------------------------- QSPI ------------------------- */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        //compatible = "flash name, "micron,m25p80";
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/*----------------------- SD1 sd2.0 -----------------------*/
&sdhci1 {
    disable-wp;
    no-1-8-v;
};


/*------------------------- ETH PHY -----------------------*/
&gem3 {
    phy-handle = <&phy0>;
    
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";
    
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};


/*----------------------- USB 2.0 only --------------------*/
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
    snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
};
    
&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};


/*---------------------------- I2C ------------------------*/
&i2c0 {
  eeprom: eeprom@50 {
     compatible = "microchip,24aa025", "atmel,24c02";
     reg = <0x50>;
     
     #address-cells = <1>;
     #size-cells = <1>;
     eth0_addr: eth-mac-addr@FA {
       reg = <0xFA 0x06>;
     };     
     
  };
};
   

FSBL patch

Must be add manually, see template

Kernel

Start with petalinux-config -c kernel

Changes:

• Only needed to fix JTAG Debug issue:

  • CONFIG_CPU_IDLE is not set

  • CONFIG_CPU_FREQ is not set

  • CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

Kernel

Start with petalinux-config -c kernel

Changes:

• Only needed to fix JTAG Debug issue:

  • CONFIG_CPU_FREQ is not set

Rootfs

Start with petalinux-config -c rootfs

Changes:

• For web server app:
  • CONFIG_busybox-httpd=y
• For additional test tools only:
  • CONFIG_i2c-tools=y
  • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
• For auto login:
  • CONFIG_auto-login=y
  • CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software

SI5338

File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices